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18982bd016bb8b070a8899374379ffe9a674796e
compute-runtime/unit_tests/libult
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Mrozek, Michal e7a4635dd6 Add mechanism to register instruction cache flushes. 
- With this mechanism csr with add pipe control with instruction cache flush
prior to enqueue, to make sure that this cache is flushed.

Change-Id: I664f212427686e9957027c7cf6c0dab17d2a3cac
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-28 07:56:41 +02:00
..
CMakeLists.txt
Refactor blit buffer call
2019-08-09 16:43:40 +02:00
create_command_stream.cpp
Refactor blit buffer call
2019-08-09 16:43:40 +02:00
create_command_stream.h
Move HardwareInfo ownership to ExecutionEnvironment [1/n]
2019-05-08 16:11:01 +02:00
create_tbx_sockets.cpp
Change namespace from OCLRT to NEO
2019-03-26 15:48:19 +01:00
gen8.cpp
Change namespace from OCLRT to NEO
2019-03-26 15:48:19 +01:00
gen9.cpp
Change namespace from OCLRT to NEO
2019-03-26 15:48:19 +01:00
gen11.cpp
Add support for Gen11 platform
2019-04-05 14:28:55 +02:00
os_interface.cpp
Disable LocalMemory in ULTs in 32 bit
2019-06-19 09:56:37 +02:00
source_level_debugger_library.cpp
Move string.h to core helpers
2019-07-19 07:21:00 +02:00
source_level_debugger_library.h
Change namespace from OCLRT to NEO
2019-03-26 15:48:19 +01:00
source_level_debugger.cpp
Change namespace from OCLRT to NEO
2019-03-26 15:48:19 +01:00
ult_aub_command_stream_receiver.h
Refactor blit buffer call
2019-08-09 16:43:40 +02:00
ult_command_stream_receiver.h
Add mechanism to register instruction cache flushes.
2019-08-28 07:56:41 +02:00