2020-03-10 12:20:24 -07:00
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//===- ControlFlowInterfaces.cpp - ControlFlow Interfaces -----------------===//
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2020-03-05 12:40:23 -08:00
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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2022-04-16 08:06:25 +00:00
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#include <utility>
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2022-06-13 22:02:02 +00:00
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#include "mlir/IR/BuiltinTypes.h"
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2020-03-10 12:20:24 -07:00
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#include "mlir/Interfaces/ControlFlowInterfaces.h"
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2020-07-15 11:12:38 -07:00
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#include "llvm/ADT/SmallPtrSet.h"
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2020-03-05 12:40:23 -08:00
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using namespace mlir;
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//===----------------------------------------------------------------------===//
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// ControlFlowInterfaces
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//===----------------------------------------------------------------------===//
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2020-03-10 12:20:24 -07:00
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#include "mlir/Interfaces/ControlFlowInterfaces.cpp.inc"
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2020-03-05 12:40:23 -08:00
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2022-04-08 08:17:36 +02:00
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SuccessorOperands::SuccessorOperands(MutableOperandRange forwardedOperands)
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2022-04-16 08:06:25 +00:00
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: producedOperandCount(0), forwardedOperands(std::move(forwardedOperands)) {
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}
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2022-04-08 08:17:36 +02:00
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SuccessorOperands::SuccessorOperands(unsigned int producedOperandCount,
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MutableOperandRange forwardedOperands)
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: producedOperandCount(producedOperandCount),
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forwardedOperands(std::move(forwardedOperands)) {}
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2020-03-05 12:40:23 -08:00
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//===----------------------------------------------------------------------===//
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// BranchOpInterface
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//===----------------------------------------------------------------------===//
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/// Returns the `BlockArgument` corresponding to operand `operandIndex` in some
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2022-12-04 19:58:32 -08:00
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/// successor if 'operandIndex' is within the range of 'operands', or
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/// std::nullopt if `operandIndex` isn't a successor operand index.
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2022-12-14 11:39:19 +01:00
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std::optional<BlockArgument>
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2022-04-08 08:17:36 +02:00
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detail::getBranchSuccessorArgument(const SuccessorOperands &operands,
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2020-07-15 11:12:38 -07:00
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unsigned operandIndex, Block *successor) {
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OperandRange forwardedOperands = operands.getForwardedOperands();
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// Check that the operands are valid.
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2022-04-08 08:17:36 +02:00
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if (forwardedOperands.empty())
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2022-12-03 18:50:27 -08:00
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return std::nullopt;
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2020-03-05 12:40:23 -08:00
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// Check to ensure that this operand is within the range.
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2022-04-08 08:17:36 +02:00
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unsigned operandsStart = forwardedOperands.getBeginOperandIndex();
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if (operandIndex < operandsStart ||
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operandIndex >= (operandsStart + forwardedOperands.size()))
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return std::nullopt;
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2020-03-05 12:40:23 -08:00
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// Index the successor.
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2022-04-08 08:17:36 +02:00
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unsigned argIndex =
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operands.getProducedOperandCount() + operandIndex - operandsStart;
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2020-03-05 12:40:23 -08:00
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return successor->getArgument(argIndex);
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}
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/// Verify that the given operands match those of the given successor block.
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LogicalResult
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2020-07-15 11:12:38 -07:00
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detail::verifyBranchSuccessorOperands(Operation *op, unsigned succNo,
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const SuccessorOperands &operands) {
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2020-03-05 12:40:23 -08:00
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// Check the count.
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unsigned operandCount = operands.size();
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Block *destBB = op->getSuccessor(succNo);
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if (operandCount != destBB->getNumArguments())
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return op->emitError() << "branch has " << operandCount
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<< " operands for successor #" << succNo
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<< ", but target block has "
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<< destBB->getNumArguments();
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// Check the types.
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2022-04-08 08:17:36 +02:00
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for (unsigned i = operands.getProducedOperandCount(); i != operandCount;
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++i) {
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[mlir] Region/BranchOpInterface: Allow implicit type conversions along control-flow edges
RegionBranchOpInterface and BranchOpInterface are allowed to make implicit type conversions along control-flow edges. In effect, this adds an interface method, `areTypesCompatible`, to both interfaces, which should return whether the types of corresponding successor operands and block arguments are compatible. Users of the interfaces, here on forth, must be aware that types may mismatch, although current users (in MLIR core), are not affected by this change. By default, type equality is used.
`async.execute` already has unequal types along control-flow edges (`!async.value<f32>` vs. `f32`), but it opted out of calling `RegionBranchOpInterface::verifyTypes` in its verifier. That method has now been removed and `RegionBranchOpInterface` will verify types along control edges by default in its verifier.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D120790
2022-03-04 20:23:24 +00:00
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if (!cast<BranchOpInterface>(op).areTypesCompatible(
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2022-04-08 08:17:36 +02:00
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operands[i].getType(), destBB->getArgument(i).getType()))
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2020-03-05 12:40:23 -08:00
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return op->emitError() << "type mismatch for bb argument #" << i
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<< " of successor #" << succNo;
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}
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return success();
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}
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2020-07-15 11:12:38 -07:00
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//===----------------------------------------------------------------------===//
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// RegionBranchOpInterface
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//===----------------------------------------------------------------------===//
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2023-08-30 09:22:34 +02:00
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static InFlightDiagnostic &printRegionEdgeName(InFlightDiagnostic &diag,
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RegionBranchPoint sourceNo,
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RegionBranchPoint succRegionNo) {
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2023-08-09 16:15:17 +02:00
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diag << "from ";
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2023-08-30 09:22:34 +02:00
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if (Region *region = sourceNo.getRegionOrNull())
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diag << "Region #" << region->getRegionNumber();
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2023-08-09 16:15:17 +02:00
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else
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diag << "parent operands";
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diag << " to ";
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2023-08-30 09:22:34 +02:00
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if (Region *region = succRegionNo.getRegionOrNull())
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diag << "Region #" << region->getRegionNumber();
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2023-08-09 16:15:17 +02:00
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else
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diag << "parent results";
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return diag;
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}
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2020-07-15 11:12:38 -07:00
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/// Verify that types match along all region control flow edges originating from
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2023-09-21 18:17:14 +02:00
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/// `sourcePoint`. `getInputsTypesForRegion` is a function that returns the
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/// types of the inputs that flow to a successor region.
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2023-08-30 09:22:34 +02:00
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static LogicalResult
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verifyTypesAlongAllEdges(Operation *op, RegionBranchPoint sourcePoint,
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function_ref<FailureOr<TypeRange>(RegionBranchPoint)>
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getInputsTypesForRegion) {
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2020-07-15 11:12:38 -07:00
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auto regionInterface = cast<RegionBranchOpInterface>(op);
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SmallVector<RegionSuccessor, 2> successors;
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regionInterface.getSuccessorRegions(sourcePoint, successors);
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2020-07-15 11:12:38 -07:00
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for (RegionSuccessor &succ : successors) {
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2023-08-30 09:22:34 +02:00
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FailureOr<TypeRange> sourceTypes = getInputsTypesForRegion(succ);
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2023-08-09 16:15:17 +02:00
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if (failed(sourceTypes))
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return failure();
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2020-11-04 09:41:55 +01:00
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2020-07-15 11:12:38 -07:00
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TypeRange succInputsTypes = succ.getSuccessorInputs().getTypes();
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2020-11-04 09:41:55 +01:00
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if (sourceTypes->size() != succInputsTypes.size()) {
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2020-07-15 11:12:38 -07:00
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InFlightDiagnostic diag = op->emitOpError(" region control flow edge ");
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2023-08-30 09:22:34 +02:00
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return printRegionEdgeName(diag, sourcePoint, succ)
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2023-08-09 16:15:17 +02:00
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<< ": source has " << sourceTypes->size()
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<< " operands, but target successor needs "
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<< succInputsTypes.size();
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2020-07-15 11:12:38 -07:00
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}
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2022-01-02 22:02:14 +00:00
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for (const auto &typesIdx :
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2020-11-04 09:41:55 +01:00
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llvm::enumerate(llvm::zip(*sourceTypes, succInputsTypes))) {
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2020-07-15 11:12:38 -07:00
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Type sourceType = std::get<0>(typesIdx.value());
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Type inputType = std::get<1>(typesIdx.value());
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[mlir] Region/BranchOpInterface: Allow implicit type conversions along control-flow edges
RegionBranchOpInterface and BranchOpInterface are allowed to make implicit type conversions along control-flow edges. In effect, this adds an interface method, `areTypesCompatible`, to both interfaces, which should return whether the types of corresponding successor operands and block arguments are compatible. Users of the interfaces, here on forth, must be aware that types may mismatch, although current users (in MLIR core), are not affected by this change. By default, type equality is used.
`async.execute` already has unequal types along control-flow edges (`!async.value<f32>` vs. `f32`), but it opted out of calling `RegionBranchOpInterface::verifyTypes` in its verifier. That method has now been removed and `RegionBranchOpInterface` will verify types along control edges by default in its verifier.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D120790
2022-03-04 20:23:24 +00:00
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if (!regionInterface.areTypesCompatible(sourceType, inputType)) {
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2020-07-15 11:12:38 -07:00
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InFlightDiagnostic diag = op->emitOpError(" along control flow edge ");
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2023-08-30 09:22:34 +02:00
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return printRegionEdgeName(diag, sourcePoint, succ)
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2020-09-08 15:49:50 -07:00
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<< ": source type #" << typesIdx.index() << " " << sourceType
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<< " should match input type #" << typesIdx.index() << " "
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2020-07-15 11:12:38 -07:00
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<< inputType;
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}
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}
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}
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return success();
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}
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/// Verify that types match along control flow edges described the given op.
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LogicalResult detail::verifyTypesAlongControlFlowEdges(Operation *op) {
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auto regionInterface = cast<RegionBranchOpInterface>(op);
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2023-09-21 18:17:14 +02:00
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auto inputTypesFromParent = [&](RegionBranchPoint point) -> TypeRange {
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return regionInterface.getEntrySuccessorOperands(point).getTypes();
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2020-07-15 11:12:38 -07:00
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};
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// Verify types along control flow edges originating from the parent.
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2023-08-30 09:22:34 +02:00
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if (failed(verifyTypesAlongAllEdges(op, RegionBranchPoint::parent(),
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inputTypesFromParent)))
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2020-07-15 11:12:38 -07:00
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return failure();
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[mlir] Region/BranchOpInterface: Allow implicit type conversions along control-flow edges
RegionBranchOpInterface and BranchOpInterface are allowed to make implicit type conversions along control-flow edges. In effect, this adds an interface method, `areTypesCompatible`, to both interfaces, which should return whether the types of corresponding successor operands and block arguments are compatible. Users of the interfaces, here on forth, must be aware that types may mismatch, although current users (in MLIR core), are not affected by this change. By default, type equality is used.
`async.execute` already has unequal types along control-flow edges (`!async.value<f32>` vs. `f32`), but it opted out of calling `RegionBranchOpInterface::verifyTypes` in its verifier. That method has now been removed and `RegionBranchOpInterface` will verify types along control edges by default in its verifier.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D120790
2022-03-04 20:23:24 +00:00
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auto areTypesCompatible = [&](TypeRange lhs, TypeRange rhs) {
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if (lhs.size() != rhs.size())
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return false;
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for (auto types : llvm::zip(lhs, rhs)) {
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if (!regionInterface.areTypesCompatible(std::get<0>(types),
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std::get<1>(types))) {
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return false;
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}
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}
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return true;
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};
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2020-07-15 11:12:38 -07:00
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// Verify types along control flow edges originating from each region.
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2023-08-30 09:22:34 +02:00
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for (Region ®ion : op->getRegions()) {
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2020-07-15 11:12:38 -07:00
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2023-08-09 16:15:17 +02:00
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// Since there can be multiple terminators implementing the
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// `RegionBranchTerminatorOpInterface`, all should have the same operand
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// types when passing them to the same region.
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2020-07-15 11:12:38 -07:00
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2023-08-09 16:15:17 +02:00
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SmallVector<RegionBranchTerminatorOpInterface> regionReturnOps;
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for (Block &block : region)
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2024-01-04 14:43:52 -06:00
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if (!block.empty())
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if (auto terminator =
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dyn_cast<RegionBranchTerminatorOpInterface>(block.back()))
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regionReturnOps.push_back(terminator);
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2020-07-15 11:12:38 -07:00
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2023-08-09 16:15:17 +02:00
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// If there is no return-like terminator, the op itself should verify
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// type consistency.
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if (regionReturnOps.empty())
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continue;
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auto inputTypesForRegion =
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2023-09-21 18:17:14 +02:00
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[&](RegionBranchPoint point) -> FailureOr<TypeRange> {
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2023-08-09 16:15:17 +02:00
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std::optional<OperandRange> regionReturnOperands;
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for (RegionBranchTerminatorOpInterface regionReturnOp : regionReturnOps) {
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2023-09-21 18:17:14 +02:00
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auto terminatorOperands = regionReturnOp.getSuccessorOperands(point);
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2023-08-09 16:15:17 +02:00
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if (!regionReturnOperands) {
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regionReturnOperands = terminatorOperands;
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continue;
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}
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// Found more than one ReturnLike terminator. Make sure the operand
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// types match with the first one.
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if (!areTypesCompatible(regionReturnOperands->getTypes(),
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terminatorOperands.getTypes())) {
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InFlightDiagnostic diag = op->emitOpError(" along control flow edge");
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2023-09-21 18:17:14 +02:00
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return printRegionEdgeName(diag, region, point)
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2023-08-09 16:15:17 +02:00
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<< " operands mismatch between return-like terminators";
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}
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}
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2020-11-04 09:41:55 +01:00
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2021-07-23 11:59:21 +02:00
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// All successors get the same set of operand types.
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return TypeRange(regionReturnOperands->getTypes());
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2020-07-15 11:12:38 -07:00
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};
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2023-08-30 09:22:34 +02:00
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if (failed(verifyTypesAlongAllEdges(op, region, inputTypesForRegion)))
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2020-07-15 11:12:38 -07:00
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return failure();
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}
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return success();
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}
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2021-07-23 11:59:21 +02:00
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2022-04-19 16:21:08 +09:00
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/// Return `true` if region `r` is reachable from region `begin` according to
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/// the RegionBranchOpInterface (by taking a branch).
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static bool isRegionReachable(Region *begin, Region *r) {
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assert(begin->getParentOp() == r->getParentOp() &&
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"expected that both regions belong to the same op");
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auto op = cast<RegionBranchOpInterface>(begin->getParentOp());
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SmallVector<bool> visited(op->getNumRegions(), false);
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visited[begin->getRegionNumber()] = true;
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// Retrieve all successors of the region and enqueue them in the worklist.
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2023-08-30 09:22:34 +02:00
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SmallVector<Region *> worklist;
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auto enqueueAllSuccessors = [&](Region *region) {
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2022-04-19 16:21:08 +09:00
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SmallVector<RegionSuccessor> successors;
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2023-08-30 09:22:34 +02:00
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op.getSuccessorRegions(region, successors);
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2022-04-19 16:21:08 +09:00
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for (RegionSuccessor successor : successors)
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if (!successor.isParent())
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2023-08-30 09:22:34 +02:00
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worklist.push_back(successor.getSuccessor());
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2022-04-19 16:21:08 +09:00
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};
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2023-08-30 09:22:34 +02:00
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enqueueAllSuccessors(begin);
|
2022-04-19 16:21:08 +09:00
|
|
|
|
|
|
|
|
// Process all regions in the worklist via DFS.
|
|
|
|
|
while (!worklist.empty()) {
|
2023-08-30 09:22:34 +02:00
|
|
|
Region *nextRegion = worklist.pop_back_val();
|
|
|
|
|
if (nextRegion == r)
|
2022-04-19 16:21:08 +09:00
|
|
|
return true;
|
2023-08-30 09:22:34 +02:00
|
|
|
if (visited[nextRegion->getRegionNumber()])
|
2022-04-19 16:21:08 +09:00
|
|
|
continue;
|
2023-08-30 09:22:34 +02:00
|
|
|
visited[nextRegion->getRegionNumber()] = true;
|
2022-04-19 16:21:08 +09:00
|
|
|
enqueueAllSuccessors(nextRegion);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2021-11-25 17:42:08 +09:00
|
|
|
/// Return `true` if `a` and `b` are in mutually exclusive regions.
|
|
|
|
|
///
|
|
|
|
|
/// 1. Find the first common of `a` and `b` (ancestor) that implements
|
|
|
|
|
/// RegionBranchOpInterface.
|
|
|
|
|
/// 2. Determine the regions `regionA` and `regionB` in which `a` and `b` are
|
|
|
|
|
/// contained.
|
|
|
|
|
/// 3. Check if `regionA` and `regionB` are mutually exclusive. They are
|
|
|
|
|
/// mutually exclusive if they are not reachable from each other as per
|
|
|
|
|
/// RegionBranchOpInterface::getSuccessorRegions.
|
|
|
|
|
bool mlir::insideMutuallyExclusiveRegions(Operation *a, Operation *b) {
|
|
|
|
|
assert(a && "expected non-empty operation");
|
|
|
|
|
assert(b && "expected non-empty operation");
|
|
|
|
|
|
|
|
|
|
auto branchOp = a->getParentOfType<RegionBranchOpInterface>();
|
|
|
|
|
while (branchOp) {
|
|
|
|
|
// Check if b is inside branchOp. (We already know that a is.)
|
|
|
|
|
if (!branchOp->isProperAncestor(b)) {
|
|
|
|
|
// Check next enclosing RegionBranchOpInterface.
|
|
|
|
|
branchOp = branchOp->getParentOfType<RegionBranchOpInterface>();
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// b is contained in branchOp. Retrieve the regions in which `a` and `b`
|
|
|
|
|
// are contained.
|
|
|
|
|
Region *regionA = nullptr, *regionB = nullptr;
|
|
|
|
|
for (Region &r : branchOp->getRegions()) {
|
|
|
|
|
if (r.findAncestorOpInRegion(*a)) {
|
|
|
|
|
assert(!regionA && "already found a region for a");
|
|
|
|
|
regionA = &r;
|
|
|
|
|
}
|
|
|
|
|
if (r.findAncestorOpInRegion(*b)) {
|
|
|
|
|
assert(!regionB && "already found a region for b");
|
|
|
|
|
regionB = &r;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
assert(regionA && regionB && "could not find region of op");
|
|
|
|
|
|
2022-04-19 16:21:08 +09:00
|
|
|
// `a` and `b` are in mutually exclusive regions if both regions are
|
|
|
|
|
// distinct and neither region is reachable from the other region.
|
|
|
|
|
return regionA != regionB && !isRegionReachable(regionA, regionB) &&
|
2021-11-25 17:42:08 +09:00
|
|
|
!isRegionReachable(regionB, regionA);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Could not find a common RegionBranchOpInterface among a's and b's
|
|
|
|
|
// ancestors.
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2022-04-19 16:12:40 +09:00
|
|
|
bool RegionBranchOpInterface::isRepetitiveRegion(unsigned index) {
|
2022-04-19 16:21:08 +09:00
|
|
|
Region *region = &getOperation()->getRegion(index);
|
|
|
|
|
return isRegionReachable(region, region);
|
2022-04-19 16:12:40 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Region *mlir::getEnclosingRepetitiveRegion(Operation *op) {
|
|
|
|
|
while (Region *region = op->getParentRegion()) {
|
|
|
|
|
op = region->getParentOp();
|
|
|
|
|
if (auto branchOp = dyn_cast<RegionBranchOpInterface>(op))
|
|
|
|
|
if (branchOp.isRepetitiveRegion(region->getRegionNumber()))
|
|
|
|
|
return region;
|
|
|
|
|
}
|
|
|
|
|
return nullptr;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Region *mlir::getEnclosingRepetitiveRegion(Value value) {
|
|
|
|
|
Region *region = value.getParentRegion();
|
|
|
|
|
while (region) {
|
|
|
|
|
Operation *op = region->getParentOp();
|
|
|
|
|
if (auto branchOp = dyn_cast<RegionBranchOpInterface>(op))
|
|
|
|
|
if (branchOp.isRepetitiveRegion(region->getRegionNumber()))
|
|
|
|
|
return region;
|
|
|
|
|
region = op->getParentRegion();
|
|
|
|
|
}
|
|
|
|
|
return nullptr;
|
|
|
|
|
}
|