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[RISCV] Fix a UBSAN failure for passing INT64_MIN to std::abs.

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clang recently started checking for INT64_MIN being passed to 64-bit std::abs.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D158304
This commit is contained in:
Craig Topper
2023-08-18 12:42:45 -07:00
parent 92e0c0dc1a
commit 078eb4bd85
1 changed files with 7 additions and 6 deletions
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13
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@@ -3232,12 +3232,13 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
bool Negate = false;
int64_t SplatStepVal = StepNumerator;
unsigned StepOpcode = ISD::MUL;
if (StepNumerator != 1) {
if (isPowerOf2_64(std::abs(StepNumerator))) {
Negate = StepNumerator < 0;
StepOpcode = ISD::SHL;
SplatStepVal = Log2_64(std::abs(StepNumerator));
}
// Exclude INT64_MIN to avoid passing it to std::abs. We won't optimize it
// anyway as the shift of 63 won't fit in uimm5.
if (StepNumerator != 1 && StepNumerator != INT64_MIN &&
isPowerOf2_64(std::abs(StepNumerator))) {
Negate = StepNumerator < 0;
StepOpcode = ISD::SHL;
SplatStepVal = Log2_64(std::abs(StepNumerator));
}
// Only emit VIDs with suitably-small steps/addends. We use imm5 is a