intel/llvm
1
0
Fork 0
mirror of https://github.com/intel/llvm.git synced 2026-01-17 06:40:01 +08:00
Code Issues Packages Projects Releases Wiki Activity

[llvm] Make use of llvm::reverse_conditionally() in a few places (NFCI) (#171150)

Browse Source
This commit is contained in:
Benjamin Maxwell
2025-12-09 09:13:58 +00:00
committed by GitHub
parent ca927e564d
commit 085dc63e3a
3 changed files with 16 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
llvm/lib/CodeGen/PrologEpilogInserter.cpp
View File

@@ -911,29 +911,18 @@ void PEIImpl::calculateFrameObjectOffsets(MachineFunction &MF) {
Align MaxAlign = MFI.getMaxAlign();
// First assign frame offsets to stack objects that are used to spill
// callee saved registers.
if (StackGrowsDown) {
for (int FI = MFI.getObjectIndexBegin(); FI < MFI.getObjectIndexEnd();
FI++) {
// Only allocate objects on the default stack.
if (!MFI.isCalleeSavedObjectIndex(FI) ||
MFI.getStackID(FI) != TargetStackID::Default)
continue;
// TODO: should we be using MFI.isDeadObjectIndex(FI) here?
AdjustStackOffset(MFI, FI, StackGrowsDown, Offset, MaxAlign);
}
} else {
for (int FI = MFI.getObjectIndexEnd() - 1; FI >= MFI.getObjectIndexBegin();
FI--) {
// Only allocate objects on the default stack.
if (!MFI.isCalleeSavedObjectIndex(FI) ||
MFI.getStackID(FI) != TargetStackID::Default)
continue;
auto AllFIs = seq(MFI.getObjectIndexBegin(), MFI.getObjectIndexEnd());
for (int FI : reverse_conditionally(AllFIs, /*Reverse=*/!StackGrowsDown)) {
// Only allocate objects on the default stack.
if (!MFI.isCalleeSavedObjectIndex(FI) ||
MFI.getStackID(FI) != TargetStackID::Default)
continue;
if (MFI.isDeadObjectIndex(FI))
continue;
// TODO: should this just be if (MFI.isDeadObjectIndex(FI))
if (!StackGrowsDown && MFI.isDeadObjectIndex(FI))
continue;
AdjustStackOffset(MFI, FI, StackGrowsDown, Offset, MaxAlign);
}
AdjustStackOffset(MFI, FI, StackGrowsDown, Offset, MaxAlign);
}
assert(MaxAlign == MFI.getMaxAlign() &&

7
llvm/lib/CodeGen/RegisterClassInfo.cpp
View File

@@ -145,12 +145,7 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
// FIXME: Once targets reserve registers instead of removing them from the
// allocation order, we can simply use begin/end here.
ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF, Reverse);
std::vector<MCPhysReg> ReverseOrder;
if (Reverse) {
llvm::append_range(ReverseOrder, reverse(RawOrder));
RawOrder = ArrayRef<MCPhysReg>(ReverseOrder);
}
for (unsigned PhysReg : RawOrder) {
for (unsigned PhysReg : reverse_conditionally(RawOrder, Reverse)) {
// Remove reserved registers from the allocation order.
if (Reserved.test(PhysReg))
continue;

17
llvm/lib/MC/MCWin64EH.cpp
View File

@@ -887,7 +887,11 @@ static void simplifyARM64Opcodes(std::vector<WinEH::Instruction> &Instructions,
unsigned PrevOffset = -1;
unsigned PrevRegister = -1;
auto VisitInstruction = [&](WinEH::Instruction &Inst) {
// Iterate over instructions in a forward order (for prologues),
// backwards for epilogues (i.e. always reverse compared to how the
// opcodes are stored).
for (WinEH::Instruction &Inst :
llvm::reverse_conditionally(Instructions, Reverse)) {
// Convert 2-byte opcodes into equivalent 1-byte ones.
if (Inst.Operation == Win64EH::UOP_SaveRegP && Inst.Register == 29) {
Inst.Operation = Win64EH::UOP_SaveFPLR;
@@ -930,17 +934,6 @@ static void simplifyARM64Opcodes(std::vector<WinEH::Instruction> &Instructions,
PrevRegister = -1;
PrevOffset = -1;
}
};
// Iterate over instructions in a forward order (for prologues),
// backwards for epilogues (i.e. always reverse compared to how the
// opcodes are stored).
if (Reverse) {
for (auto It = Instructions.rbegin(); It != Instructions.rend(); It++)
VisitInstruction(*It);
} else {
for (WinEH::Instruction &Inst : Instructions)
VisitInstruction(Inst);
}
}