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[AArch64] Add a performBICiCombine function.

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This moves the code out of PerformDAGCombine directly, changing the return
to return SDValue(N, 0) to match other uses of SimplifyDemandedBits.
This commit is contained in:
David Green
2025-12-15 07:23:31 +00:00
parent 6ff3df87d1
commit 1e9e38983c
1 changed files with 15 additions and 12 deletions
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27
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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@@ -19598,6 +19598,19 @@ static SDValue performUADDVCombine(SDNode *N, SelectionDAG &DAG) {
return SDValue();
}
static SDValue performBICiCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI) {
APInt DemandedBits =
APInt::getAllOnes(N->getValueType(0).getScalarSizeInBits());
APInt DemandedElts =
APInt::getAllOnes(N->getValueType(0).getVectorNumElements());
if (DAG.getTargetLoweringInfo().SimplifyDemandedBits(
SDValue(N, 0), DemandedBits, DemandedElts, DCI))
return SDValue(N, 0);
return SDValue();
}
static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const AArch64Subtarget *Subtarget) {
@@ -28399,18 +28412,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
return performFlagSettingCombine(N, DCI, ISD::ADD);
case AArch64ISD::SUBS:
return performFlagSettingCombine(N, DCI, ISD::SUB);
case AArch64ISD::BICi: {
APInt DemandedBits =
APInt::getAllOnes(N->getValueType(0).getScalarSizeInBits());
APInt DemandedElts =
APInt::getAllOnes(N->getValueType(0).getVectorNumElements());
if (DAG.getTargetLoweringInfo().SimplifyDemandedBits(
SDValue(N, 0), DemandedBits, DemandedElts, DCI))
return SDValue();
break;
}
case AArch64ISD::BICi:
return performBICiCombine(N, DAG, DCI);
case ISD::XOR:
return performXorCombine(N, DAG, DCI, Subtarget);
case ISD::MUL: