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[SPIR-V] Stop using Register to represent target specific virtual registers. (#129362)

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These were using the virtual register encoding in Register which
required including Register.h in MC layer code which is a layering
violation.

This also required converting Register with bit 31 set to MCRegister
which should be an error. Register with bit 31 set should only be used
for codegen virtual register. I'd like to add assertions to enforce
this.

Migrate to MCRegister and manually create an encoding with bit 31 set.
WebAssembly also does this.

We could consider adding interfaces to MCRegister for target specific
virtual registers.
This commit is contained in:
Craig Topper
2025-03-03 08:43:02 -08:00
committed by GitHub
parent 47c255b3e7
commit 201208998f
7 changed files with 65 additions and 53 deletions
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5
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
View File

@@ -14,7 +14,6 @@
#include "SPIRV.h"
#include "SPIRVBaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
@@ -97,7 +96,7 @@ void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
}
void SPIRVInstPrinter::recordOpExtInstImport(const MCInst *MI) {
Register Reg = MI->getOperand(0).getReg();
MCRegister Reg = MI->getOperand(0).getReg();
auto Name = getSPIRVStringOperand(*MI, 1);
auto Set = getExtInstSetFromString(Name);
ExtInstSetIDs.insert({Reg, Set});
@@ -335,7 +334,7 @@ void SPIRVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
if (OpNo < MI->getNumOperands()) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg())
O << '%' << (Register(Op.getReg()).virtRegIndex() + 1);
O << '%' << (getIDFromRegister(Op.getReg().id()) + 1);
else if (Op.isImm())
O << formatImm((int64_t)Op.getImm());
else if (Op.isDFPImm())

4
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
View File

@@ -11,7 +11,6 @@
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/SPIRVMCTargetDesc.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h"
@@ -77,7 +76,8 @@ static void emitOperand(const MCOperand &Op, SmallVectorImpl<char> &CB) {
if (Op.isReg()) {
// Emit the id index starting at 1 (0 is an invalid index).
support::endian::write<uint32_t>(
CB, Register(Op.getReg()).virtRegIndex() + 1, llvm::endianness::little);
CB, SPIRV::getIDFromRegister(Op.getReg().id()) + 1,
llvm::endianness::little);
} else if (Op.isImm()) {
support::endian::write(CB, static_cast<uint32_t>(Op.getImm()),
llvm::endianness::little);

8
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.h
View File

@@ -14,6 +14,7 @@
#define LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H
#include "llvm/Support/DataTypes.h"
#include <cassert>
#include <memory>
namespace llvm {
@@ -50,4 +51,11 @@ std::unique_ptr<MCObjectTargetWriter> createSPIRVObjectTargetWriter();
#define GET_SUBTARGETINFO_ENUM
#include "SPIRVGenSubtargetInfo.inc"
namespace llvm::SPIRV {
inline unsigned getIDFromRegister(unsigned Reg) {
assert(Reg & (1U << 31));
return Reg & ~(1U << 31);
}
} // namespace llvm::SPIRV
#endif // LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H

22
llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
View File

@@ -70,11 +70,11 @@ public:
void outputOpMemoryModel();
void outputOpFunctionEnd();
void outputExtFuncDecls();
void outputExecutionModeFromMDNode(Register Reg, MDNode *Node,
void outputExecutionModeFromMDNode(MCRegister Reg, MDNode *Node,
SPIRV::ExecutionMode::ExecutionMode EM,
unsigned ExpectMDOps, int64_t DefVal);
void outputExecutionModeFromNumthreadsAttribute(
const Register &Reg, const Attribute &Attr,
const MCRegister &Reg, const Attribute &Attr,
SPIRV::ExecutionMode::ExecutionMode EM);
void outputExecutionMode(const Module &M);
void outputAnnotations(const Module &M);
@@ -316,7 +316,7 @@ void SPIRVAsmPrinter::outputDebugSourceAndStrings(const Module &M) {
void SPIRVAsmPrinter::outputOpExtInstImports(const Module &M) {
for (auto &CU : MAI->ExtInstSetMap) {
unsigned Set = CU.first;
Register Reg = CU.second;
MCRegister Reg = CU.second;
MCInst Inst;
Inst.setOpcode(SPIRV::OpExtInstImport);
Inst.addOperand(MCOperand::createReg(Reg));
@@ -341,7 +341,7 @@ void SPIRVAsmPrinter::outputOpMemoryModel() {
// the interface of this entry point.
void SPIRVAsmPrinter::outputEntryPoints() {
// Find all OpVariable IDs with required StorageClass.
DenseSet<Register> InterfaceIDs;
DenseSet<MCRegister> InterfaceIDs;
for (const MachineInstr *MI : MAI->GlobalVarList) {
assert(MI->getOpcode() == SPIRV::OpVariable);
auto SC = static_cast<SPIRV::StorageClass::StorageClass>(
@@ -353,7 +353,7 @@ void SPIRVAsmPrinter::outputEntryPoints() {
if (ST->isAtLeastSPIRVVer(VersionTuple(1, 4)) ||
SC == SPIRV::StorageClass::Input || SC == SPIRV::StorageClass::Output) {
const MachineFunction *MF = MI->getMF();
Register Reg = MAI->getRegisterAlias(MF, MI->getOperand(0).getReg());
MCRegister Reg = MAI->getRegisterAlias(MF, MI->getOperand(0).getReg());
InterfaceIDs.insert(Reg);
}
}
@@ -363,7 +363,7 @@ void SPIRVAsmPrinter::outputEntryPoints() {
SPIRVMCInstLower MCInstLowering;
MCInst TmpInst;
MCInstLowering.lower(MI, TmpInst, MAI);
for (Register Reg : InterfaceIDs) {
for (MCRegister Reg : InterfaceIDs) {
assert(Reg.isValid());
TmpInst.addOperand(MCOperand::createReg(Reg));
}
@@ -444,7 +444,7 @@ static void addOpsFromMDNode(MDNode *MDN, MCInst &Inst,
if (ConstantInt *Const = dyn_cast<ConstantInt>(C)) {
Inst.addOperand(MCOperand::createImm(Const->getZExtValue()));
} else if (auto *CE = dyn_cast<Function>(C)) {
Register FuncReg = MAI->getFuncReg(CE);
MCRegister FuncReg = MAI->getFuncReg(CE);
assert(FuncReg.isValid());
Inst.addOperand(MCOperand::createReg(FuncReg));
}
@@ -453,7 +453,7 @@ static void addOpsFromMDNode(MDNode *MDN, MCInst &Inst,
}
void SPIRVAsmPrinter::outputExecutionModeFromMDNode(
Register Reg, MDNode *Node, SPIRV::ExecutionMode::ExecutionMode EM,
MCRegister Reg, MDNode *Node, SPIRV::ExecutionMode::ExecutionMode EM,
unsigned ExpectMDOps, int64_t DefVal) {
MCInst Inst;
Inst.setOpcode(SPIRV::OpExecutionMode);
@@ -470,7 +470,7 @@ void SPIRVAsmPrinter::outputExecutionModeFromMDNode(
}
void SPIRVAsmPrinter::outputExecutionModeFromNumthreadsAttribute(
const Register &Reg, const Attribute &Attr,
const MCRegister &Reg, const Attribute &Attr,
SPIRV::ExecutionMode::ExecutionMode EM) {
assert(Attr.isValid() && "Function called with an invalid attribute.");
@@ -508,7 +508,7 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
// <Entry Point> operands of OpExecutionMode
if (F.isDeclaration() || !isEntryPoint(F))
continue;
Register FReg = MAI->getFuncReg(&F);
MCRegister FReg = MAI->getFuncReg(&F);
assert(FReg.isValid());
if (MDNode *Node = F.getMetadata("reqd_work_group_size"))
outputExecutionModeFromMDNode(FReg, Node, SPIRV::ExecutionMode::LocalSize,
@@ -560,7 +560,7 @@ void SPIRVAsmPrinter::outputAnnotations(const Module &M) {
if (!isa<Function>(AnnotatedVar))
report_fatal_error("Unsupported value in llvm.global.annotations");
Function *Func = cast<Function>(AnnotatedVar);
Register Reg = MAI->getFuncReg(Func);
MCRegister Reg = MAI->getFuncReg(Func);
if (!Reg.isValid()) {
std::string DiagMsg;
raw_string_ostream OS(DiagMsg);

9
llvm/lib/Target/SPIRV/SPIRVMCInstLower.cpp
View File

@@ -34,7 +34,7 @@ void SPIRVMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI,
default:
llvm_unreachable("unknown operand type");
case MachineOperand::MO_GlobalAddress: {
Register FuncReg = MAI->getFuncReg(dyn_cast<Function>(MO.getGlobal()));
MCRegister FuncReg = MAI->getFuncReg(dyn_cast<Function>(MO.getGlobal()));
if (!FuncReg.isValid()) {
std::string DiagMsg;
raw_string_ostream OS(DiagMsg);
@@ -49,13 +49,14 @@ void SPIRVMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI,
MCOp = MCOperand::createReg(MAI->getOrCreateMBBRegister(*MO.getMBB()));
break;
case MachineOperand::MO_Register: {
Register NewReg = MAI->getRegisterAlias(MF, MO.getReg());
MCOp = MCOperand::createReg(NewReg.isValid() ? NewReg : MO.getReg());
MCRegister NewReg = MAI->getRegisterAlias(MF, MO.getReg());
MCOp = MCOperand::createReg(NewReg.isValid() ? NewReg
: MO.getReg().asMCReg());
break;
}
case MachineOperand::MO_Immediate:
if (MI->getOpcode() == SPIRV::OpExtInst && i == 2) {
Register Reg = MAI->getExtInstSetReg(MO.getImm());
MCRegister Reg = MAI->getExtInstSetReg(MO.getImm());
MCOp = MCOperand::createReg(Reg);
} else {
MCOp = MCOperand::createImm(MO.getImm());

33
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
View File

@@ -213,8 +213,7 @@ void SPIRVModuleAnalysis::setBaseInfo(const Module &M) {
if (ST->isOpenCLEnv()) {
// TODO: check if it's required by default.
MAI.ExtInstSetMap[static_cast<unsigned>(
SPIRV::InstructionSet::OpenCL_std)] =
Register::index2VirtReg(MAI.getNextID());
SPIRV::InstructionSet::OpenCL_std)] = MAI.getNextIDRegister();
}
}
@@ -306,7 +305,8 @@ void SPIRVModuleAnalysis::visitFunPtrUse(
} while (OpDefMI && (OpDefMI->getOpcode() == SPIRV::OpFunction ||
OpDefMI->getOpcode() == SPIRV::OpFunctionParameter));
// associate the function pointer with the newly assigned global number
Register GlobalFunDefReg = MAI.getRegisterAlias(FunDefMF, OpFunDef->getReg());
MCRegister GlobalFunDefReg =
MAI.getRegisterAlias(FunDefMF, OpFunDef->getReg());
assert(GlobalFunDefReg.isValid() &&
"Function definition must refer to a global register");
MAI.setRegisterAlias(MF, OpReg, GlobalFunDefReg);
@@ -353,10 +353,10 @@ void SPIRVModuleAnalysis::visitDecl(
"No unique definition is found for the virtual register");
}
Register GReg;
MCRegister GReg;
bool IsFunDef = false;
if (TII->isSpecConstantInstr(MI)) {
GReg = Register::index2VirtReg(MAI.getNextID());
GReg = MAI.getNextIDRegister();
MAI.MS[SPIRV::MB_TypeConstVars].push_back(&MI);
} else if (Opcode == SPIRV::OpFunction ||
Opcode == SPIRV::OpFunctionParameter) {
@@ -366,7 +366,7 @@ void SPIRVModuleAnalysis::visitDecl(
const MachineInstr *NextInstr = MI.getNextNode();
while (NextInstr &&
NextInstr->getOpcode() == SPIRV::OpTypeStructContinuedINTEL) {
Register Tmp = handleTypeDeclOrConstant(*NextInstr, SignatureToGReg);
MCRegister Tmp = handleTypeDeclOrConstant(*NextInstr, SignatureToGReg);
MAI.setRegisterAlias(MF, NextInstr->getOperand(0).getReg(), Tmp);
MAI.setSkipEmission(NextInstr);
NextInstr = NextInstr->getNextNode();
@@ -389,7 +389,7 @@ void SPIRVModuleAnalysis::visitDecl(
MAI.setSkipEmission(&MI);
}
Register SPIRVModuleAnalysis::handleFunctionOrParameter(
MCRegister SPIRVModuleAnalysis::handleFunctionOrParameter(
const MachineFunction *MF, const MachineInstr &MI,
std::map<const Value *, unsigned> &GlobalToGReg, bool &IsFunDef) {
const Value *GObj = GR->getGlobalObject(MF, MI.getOperand(0).getReg());
@@ -402,27 +402,27 @@ Register SPIRVModuleAnalysis::handleFunctionOrParameter(
auto It = GlobalToGReg.find(GObj);
if (It != GlobalToGReg.end())
return It->second;
Register GReg = Register::index2VirtReg(MAI.getNextID());
MCRegister GReg = MAI.getNextIDRegister();
GlobalToGReg[GObj] = GReg;
if (!IsFunDef)
MAI.MS[SPIRV::MB_ExtFuncDecls].push_back(&MI);
return GReg;
}
Register
MCRegister
SPIRVModuleAnalysis::handleTypeDeclOrConstant(const MachineInstr &MI,
InstrGRegsMap &SignatureToGReg) {
InstrSignature MISign = instrToSignature(MI, MAI, false);
auto It = SignatureToGReg.find(MISign);
if (It != SignatureToGReg.end())
return It->second;
Register GReg = Register::index2VirtReg(MAI.getNextID());
MCRegister GReg = MAI.getNextIDRegister();
SignatureToGReg[MISign] = GReg;
MAI.MS[SPIRV::MB_TypeConstVars].push_back(&MI);
return GReg;
}
Register SPIRVModuleAnalysis::handleVariable(
MCRegister SPIRVModuleAnalysis::handleVariable(
const MachineFunction *MF, const MachineInstr &MI,
std::map<const Value *, unsigned> &GlobalToGReg) {
MAI.GlobalVarList.push_back(&MI);
@@ -431,7 +431,7 @@ Register SPIRVModuleAnalysis::handleVariable(
auto It = GlobalToGReg.find(GObj);
if (It != GlobalToGReg.end())
return It->second;
Register GReg = Register::index2VirtReg(MAI.getNextID());
MCRegister GReg = MAI.getNextIDRegister();
GlobalToGReg[GObj] = GReg;
MAI.MS[SPIRV::MB_TypeConstVars].push_back(&MI);
return GReg;
@@ -507,7 +507,7 @@ void SPIRVModuleAnalysis::collectFuncNames(MachineInstr &MI,
} else if (MI.getOpcode() == SPIRV::OpFunction) {
// Record all internal OpFunction declarations.
Register Reg = MI.defs().begin()->getReg();
Register GlobalReg = MAI.getRegisterAlias(MI.getMF(), Reg);
MCRegister GlobalReg = MAI.getRegisterAlias(MI.getMF(), Reg);
assert(GlobalReg.isValid());
MAI.FuncMap[F] = GlobalReg;
}
@@ -599,14 +599,14 @@ void SPIRVModuleAnalysis::numberRegistersGlobally(const Module &M) {
Register Reg = Op.getReg();
if (MAI.hasRegisterAlias(MF, Reg))
continue;
Register NewReg = Register::index2VirtReg(MAI.getNextID());
MCRegister NewReg = MAI.getNextIDRegister();
MAI.setRegisterAlias(MF, Reg, NewReg);
}
if (MI.getOpcode() != SPIRV::OpExtInst)
continue;
auto Set = MI.getOperand(2).getImm();
if (!MAI.ExtInstSetMap.contains(Set))
MAI.ExtInstSetMap[Set] = Register::index2VirtReg(MAI.getNextID());
MAI.ExtInstSetMap[Set] = MAI.getNextIDRegister();
}
}
}
@@ -1938,7 +1938,7 @@ static void addMBBNames(const Module &M, const SPIRVInstrInfo &TII,
Register Reg = MRI.createGenericVirtualRegister(LLT::scalar(64));
MRI.setRegClass(Reg, &SPIRV::IDRegClass);
buildOpName(Reg, MBB.getName(), *std::prev(MBB.end()), TII);
Register GlobalReg = MAI.getOrCreateMBBRegister(MBB);
MCRegister GlobalReg = MAI.getOrCreateMBBRegister(MBB);
MAI.setRegisterAlias(MF, Reg, GlobalReg);
}
}
@@ -1992,6 +1992,7 @@ bool SPIRVModuleAnalysis::runOnModule(Module &M) {
// Process type/const/global var/func decl instructions, number their
// destination registers from 0 to N, collect Extensions and Capabilities.
collectReqs(M, MAI, MMI, *ST);
collectDeclarations(M);
// Number rest of registers from N+1 onwards.

37
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h
View File

@@ -126,7 +126,7 @@ public:
using InstrList = SmallVector<const MachineInstr *>;
// Maps a local register to the corresponding global alias.
using LocalToGlobalRegTable = std::map<Register, Register>;
using LocalToGlobalRegTable = std::map<Register, MCRegister>;
using RegisterAliasMapTy =
std::map<const MachineFunction *, LocalToGlobalRegTable>;
@@ -140,11 +140,11 @@ struct ModuleAnalysisInfo {
unsigned SrcLangVersion;
StringSet<> SrcExt;
// Maps ExtInstSet to corresponding ID register.
DenseMap<unsigned, Register> ExtInstSetMap;
DenseMap<unsigned, MCRegister> ExtInstSetMap;
// Contains the list of all global OpVariables in the module.
SmallVector<const MachineInstr *, 4> GlobalVarList;
// Maps functions to corresponding function ID registers.
DenseMap<const Function *, Register> FuncMap;
DenseMap<const Function *, MCRegister> FuncMap;
// The set contains machine instructions which are necessary
// for correct MIR but will not be emitted in function bodies.
DenseSet<const MachineInstr *> InstrsToDelete;
@@ -157,29 +157,29 @@ struct ModuleAnalysisInfo {
// The array contains lists of MIs for each module section.
InstrList MS[NUM_MODULE_SECTIONS];
// The table maps MBB number to SPIR-V unique ID register.
DenseMap<std::pair<const MachineFunction *, int>, Register> BBNumToRegMap;
DenseMap<std::pair<const MachineFunction *, int>, MCRegister> BBNumToRegMap;
Register getFuncReg(const Function *F) {
MCRegister getFuncReg(const Function *F) {
assert(F && "Function is null");
auto FuncPtrRegPair = FuncMap.find(F);
return FuncPtrRegPair == FuncMap.end() ? Register(0)
return FuncPtrRegPair == FuncMap.end() ? MCRegister()
: FuncPtrRegPair->second;
}
Register getExtInstSetReg(unsigned SetNum) { return ExtInstSetMap[SetNum]; }
MCRegister getExtInstSetReg(unsigned SetNum) { return ExtInstSetMap[SetNum]; }
InstrList &getMSInstrs(unsigned MSType) { return MS[MSType]; }
void setSkipEmission(const MachineInstr *MI) { InstrsToDelete.insert(MI); }
bool getSkipEmission(const MachineInstr *MI) {
return InstrsToDelete.contains(MI);
}
void setRegisterAlias(const MachineFunction *MF, Register Reg,
Register AliasReg) {
MCRegister AliasReg) {
RegisterAliasTable[MF][Reg] = AliasReg;
}
Register getRegisterAlias(const MachineFunction *MF, Register Reg) {
MCRegister getRegisterAlias(const MachineFunction *MF, Register Reg) {
auto &RegTable = RegisterAliasTable[MF];
auto RI = RegTable.find(Reg);
if (RI == RegTable.end()) {
return Register(0);
return MCRegister();
}
return RI->second;
}
@@ -190,16 +190,19 @@ struct ModuleAnalysisInfo {
return RI->second.find(Reg) != RI->second.end();
}
unsigned getNextID() { return MaxID++; }
MCRegister getNextIDRegister() {
return MCRegister((1U << 31) | getNextID());
}
bool hasMBBRegister(const MachineBasicBlock &MBB) {
auto Key = std::make_pair(MBB.getParent(), MBB.getNumber());
return BBNumToRegMap.contains(Key);
}
// Convert MBB's number to corresponding ID register.
Register getOrCreateMBBRegister(const MachineBasicBlock &MBB) {
MCRegister getOrCreateMBBRegister(const MachineBasicBlock &MBB) {
auto Key = std::make_pair(MBB.getParent(), MBB.getNumber());
auto [It, Inserted] = BBNumToRegMap.try_emplace(Key);
if (Inserted)
It->second = Register::index2VirtReg(getNextID());
It->second = getNextIDRegister();
return It->second;
}
};
@@ -230,11 +233,11 @@ private:
void visitDecl(const MachineRegisterInfo &MRI, InstrGRegsMap &SignatureToGReg,
std::map<const Value *, unsigned> &GlobalToGReg,
const MachineFunction *MF, const MachineInstr &MI);
Register handleVariable(const MachineFunction *MF, const MachineInstr &MI,
std::map<const Value *, unsigned> &GlobalToGReg);
Register handleTypeDeclOrConstant(const MachineInstr &MI,
InstrGRegsMap &SignatureToGReg);
Register
MCRegister handleVariable(const MachineFunction *MF, const MachineInstr &MI,
std::map<const Value *, unsigned> &GlobalToGReg);
MCRegister handleTypeDeclOrConstant(const MachineInstr &MI,
InstrGRegsMap &SignatureToGReg);
MCRegister
handleFunctionOrParameter(const MachineFunction *MF, const MachineInstr &MI,
std::map<const Value *, unsigned> &GlobalToGReg,
bool &IsFunDef);