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[X86][APX] Add pattern for zext(X86setcc ..) -> SETZUCCr (#170806)

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Phoebe Wang
2025-12-05 18:06:07 +08:00
committed by GitHub
parent 5a74f7ea99
commit 2612dc9b5f
2 changed files with 17 additions and 1 deletions
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6
llvm/lib/Target/X86/X86InstrCMovSetCC.td
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@@ -150,7 +150,7 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
// SetZUCC and promoted SetCC instructions.
let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1,
hasSideEffects = 0, Predicates = [In64BitMode], Predicates = [HasNDD] in {
hasSideEffects = 0, Predicates = [In64BitMode] in {
def SETZUCCr : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
"setzu${cond}\t$dst", []>,
XD, ZU, NoCD8, Sched<[WriteSETCC]>;
@@ -167,6 +167,10 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1,
}
}
let Predicates = [HasZU] in
def : Pat<(i32 (zext (X86setcc timm:$cond, EFLAGS))),
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SETZUCCr ccode:$cond), sub_8bit)>;
// SALC is an undocumented instruction. Information for this instruction can be found
// here http://www.rcollins.org/secrets/opcodes/SALC.html
// Set AL if carry.

12
llvm/test/CodeGen/X86/apx/setzucc.ll
View File

@@ -89,3 +89,15 @@ bb1:
bb2:
ret i32 0
}
define i32 @highmask_i32_mask32(i32 %val) {
; CHECK-LABEL: highmask_i32_mask32:
; CHECK: # %bb.0:
; CHECK-NEXT: testl $-1048576, %edi # imm = 0xFFF00000
; CHECK-NEXT: setzune %al
; CHECK-NEXT: retq
%and = and i32 %val, -1048576
%cmp = icmp ne i32 %and, 0
%ret = zext i1 %cmp to i32
ret i32 %ret
}