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[RISCV] Add support of Sdext,Sdtrig extentions (#120936)

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`Sdext` and `Sdtrig` are RISC-V extensions related to debugging.

The full specification can be found at

https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf
This commit is contained in:
Shao-Ce SUN
2025-01-03 17:25:42 +08:00
committed by GitHub
parent 2582568217
commit 2fae5bdea7
11 changed files with 87 additions and 0 deletions
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2
clang/test/Driver/print-supported-extensions-riscv.c
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@@ -185,6 +185,8 @@
// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger)
// CHECK-NEXT: sdtrig 1.0 'Sdtrig' (Debugger triggers)
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)

18
clang/test/Preprocessor/riscv-target-features.c
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@@ -182,6 +182,8 @@
// Experimental extensions
// CHECK-NOT: __riscv_sdext{{.*$}}
// CHECK-NOT: __riscv_sdtrig{{.*$}}
// CHECK-NOT: __riscv_smctr{{.*$}}
// CHECK-NOT: __riscv_smmpm{{.*$}}
// CHECK-NOT: __riscv_smnpm{{.*$}}
@@ -1795,6 +1797,22 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
// CHECK-SUPM-EXT: __riscv_supm 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_sdext1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SDEXT-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_sdext1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SDEXT-EXT %s
// CHECK-SDEXT-EXT: __riscv_sdext 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_sdtrig1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SDTRIG-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_sdtrig1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SDTRIG-EXT %s
// CHECK-SDTRIG-EXT: __riscv_sdtrig 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_smctr1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCTR-EXT %s

3
llvm/docs/RISCVUsage.rst
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@@ -326,6 +326,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zvbc32e``, ``experimental-zvkgs``
LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__.
``experimental-sdext``, ``experimental-sdtrig``
LLVM implements the `1.0-rc4 specification <https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf>`__.
``experimental-smctr``, ``experimental-ssctr``
LLVM implements the `1.0-rc3 specification <https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3>`__.

1
llvm/docs/ReleaseNotes.md
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@@ -232,6 +232,7 @@ Changes to the RISC-V Backend
extension.
* Adds experimental assembler support for the Qualcomm uC 'Xqcicli` (Conditional Load Immediate)
extension.
* Added ``Sdext`` and ``Sdtrig`` extensions.
Changes to the WebAssembly Backend
----------------------------------

4
llvm/lib/Target/RISCV/RISCVFeatures.td
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@@ -844,6 +844,10 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
// Supervisor extensions
def FeatureStdExtSdext : RISCVExperimentalExtension<1, 0, "External debugger">;
def FeatureStdExtSdtrig : RISCVExperimentalExtension<1, 0, "Debugger triggers">;
def FeatureStdExtShgatpa
: RISCVExtension<1, 0,
"SvNNx4 mode supported for all modes supported by satp, as well as Bare">;

3
llvm/lib/Target/RISCV/RISCVSystemOperands.td
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@@ -323,7 +323,10 @@ def : SysReg<"tselect", 0x7A0>;
def : SysReg<"tdata1", 0x7A1>;
def : SysReg<"tdata2", 0x7A2>;
def : SysReg<"tdata3", 0x7A3>;
def : SysReg<"tinfo", 0x7A4>;
def : SysReg<"tcontrol", 0x7A5>;
def : SysReg<"mcontext", 0x7A8>;
def : SysReg<"mscontext", 0x7AA>;
//===----------------------------------------------------------------------===//
// Debug Mode Registers

4
llvm/test/CodeGen/RISCV/attributes.ll
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@@ -296,6 +296,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; Tests for profile features.
; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
@@ -605,6 +607,8 @@
; RV64SUPM: .attribute 5, "rv64i2p1_supm1p0"
; RV64SMCTR: .attribute 5, "rv64i2p1_smctr1p0_sscsrind1p0"
; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0"
; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0"
; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
; RVI20U32: .attribute 5, "rv32i2p1"
; RVI20U64: .attribute 5, "rv64i2p1"

2
llvm/test/CodeGen/RISCV/features-info.ll
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@@ -15,6 +15,8 @@
; CHECK: e - 'E' (Embedded Instruction Set with 16 GPRs).
; CHECK: experimental - Experimental intrinsics.
; CHECK: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
; CHECK: experimental-sdext - 'Sdext' (External debugger).
; CHECK: experimental-sdtrig - 'Sdtrig' (Debugger triggers).
; CHECK: experimental-smctr - 'Smctr' (Control Transfer Records Machine Level).
; CHECK: experimental-ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).
; CHECK: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).

6
llvm/test/MC/RISCV/attribute-arch.s
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@@ -467,3 +467,9 @@
.attribute arch, "rv32i_ssctr1p0"
# CHECK: attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"
.attribute arch, "rv32i_sdext1p0"
# CHECK: attribute 5, "rv32i2p1_sdext1p0"
.attribute arch, "rv32i_sdtrig1p0"
# CHECK: attribute 5, "rv32i2p1_sdtrig1p0"

42
llvm/test/MC/RISCV/machine-csr-names.s
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@@ -1419,6 +1419,34 @@ csrrs t1, tdata3, zero
# uimm12
csrrs t2, 0x7A3, zero
# tinfo
# name
# CHECK-INST: csrrs t1, tinfo, zero
# CHECK-ENC: encoding: [0x73,0x23,0x40,0x7a]
# CHECK-INST-ALIAS: csrr t1, tinfo
# uimm12
# CHECK-INST: csrrs t2, tinfo, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7a]
# CHECK-INST-ALIAS: csrr t2, tinfo
# name
csrrs t1, tinfo, zero
# uimm12
csrrs t2, 0x7A4, zero
# tcontrol
# name
# CHECK-INST: csrrs t1, tcontrol, zero
# CHECK-ENC: encoding: [0x73,0x23,0x50,0x7a]
# CHECK-INST-ALIAS: csrr t1, tcontrol
# uimm12
# CHECK-INST: csrrs t2, tcontrol, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7a]
# CHECK-INST-ALIAS: csrr t2, tcontrol
# name
csrrs t1, tcontrol, zero
# uimm12
csrrs t2, 0x7A5, zero
# mcontext
# name
# CHECK-INST: csrrs t1, mcontext, zero
@@ -1433,6 +1461,20 @@ csrrs t1, mcontext, zero
# uimm12
csrrs t2, 0x7A8, zero
# mscontext
# name
# CHECK-INST: csrrs t1, mscontext, zero
# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x7a]
# CHECK-INST-ALIAS: csrr t1, mscontext
# uimm12
# CHECK-INST: csrrs t2, mscontext, zero
# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x7a]
# CHECK-INST-ALIAS: csrr t2, mscontext
# name
csrrs t1, mscontext, zero
# uimm12
csrrs t2, 0x7AA, zero
#######################
# Debug Mode Registers
########################

2
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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@@ -1110,6 +1110,8 @@ Experimental extensions
zalasr 0.1
zvbc32e 0.7
zvkgs 0.7
sdext 1.0
sdtrig 1.0
smctr 1.0
ssctr 1.0
svukte 0.3