intel/llvm
1
0
Fork 0
mirror of https://github.com/intel/llvm.git synced 2026-01-16 05:32:28 +08:00
Code Issues Packages Projects Releases Wiki Activity

[RISCV] Remove now unused immzero operand type. NFC

Browse Source
This commit is contained in:
Craig Topper
2025-07-25 21:16:07 -07:00
parent f1cd0cd6ea
commit 359c04a61c
3 changed files with 0 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
View File

@@ -330,7 +330,6 @@ enum OperandType : unsigned {
OPERAND_UIMM32,
OPERAND_UIMM48,
OPERAND_UIMM64,
OPERAND_ZERO,
OPERAND_THREE,
OPERAND_FOUR,
OPERAND_SIMM5,

3
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
View File

@@ -2859,9 +2859,6 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_UIMM16_NONZERO:
Ok = isUInt<16>(Imm) && (Imm != 0);
break;
case RISCVOp::OPERAND_ZERO:
Ok = Imm == 0;
break;
case RISCVOp::OPERAND_THREE:
Ok = Imm == 3;
break;

6
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
View File

@@ -57,12 +57,6 @@ def simm6nonzero : RISCVOp,
}];
}
def immzero : RISCVOp,
ImmLeaf<XLenVT, [{return (Imm == 0);}]> {
let ParserMatchClass = ImmZeroAsmOperand;
let OperandType = "OPERAND_ZERO";
}
def CLUIImmAsmOperand : AsmOperandClass {
let Name = "CLUIImm";
let RenderMethod = "addImmOperands";