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[BOLT][NFC] Infailable fns return void (#92018)

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Both `reverseBranchCondition` and `replaceBranchTarget` return a success boolean. But all-but-one caller ignores the return value, and the exception emits a fatal error on failure.

Thus, just return nothing.
This commit is contained in:
Nathan Sidwell
2024-06-07 06:59:52 -04:00
committed by GitHub
parent 88e2bb4092
commit 3fefb3c598
5 changed files with 12 additions and 25 deletions
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10
bolt/include/bolt/Core/MCPlusBuilder.h
View File

@@ -1706,12 +1706,9 @@ public:
}
/// Reverses the branch condition in Inst and update its taken target to TBB.
///
/// Returns true on success.
virtual bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
virtual void reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const {
llvm_unreachable("not implemented");
return false;
}
virtual bool replaceBranchCondition(MCInst &Inst, const MCSymbol *TBB,
@@ -1751,12 +1748,9 @@ public:
}
/// Sets the taken target of the branch instruction to Target.
///
/// Returns true on success.
virtual bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
virtual void replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const {
llvm_unreachable("not implemented");
return false;
}
/// Extract a symbol and an addend out of the fixup value expression.

7
bolt/lib/Passes/VeneerElimination.cpp
View File

@@ -77,11 +77,8 @@ Error VeneerElimination::runOnFunctions(BinaryContext &BC) {
continue;
VeneerCallers++;
if (!BC.MIB->replaceBranchTarget(
Instr, VeneerDestinations[TargetSymbol], BC.Ctx.get())) {
return createFatalBOLTError(
"BOLT-ERROR: updating veneer call destination failed\n");
}
BC.MIB->replaceBranchTarget(Instr, VeneerDestinations[TargetSymbol],
BC.Ctx.get());
}
}
}

7
bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
View File

@@ -616,7 +616,7 @@ public:
return getTargetAddend(Op.getExpr());
}
bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
void replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) &&
"Invalid instruction");
@@ -638,7 +638,6 @@ public:
*OI = MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx));
return true;
}
/// Matches indirect branch patterns in AArch64 related to a jump table (JT),
@@ -969,7 +968,7 @@ public:
}
}
bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
void reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
if (isTB(Inst) || isCB(Inst)) {
Inst.setOpcode(getInvertedBranchOpcode(Inst.getOpcode()));
@@ -984,7 +983,7 @@ public:
LLVM_DEBUG(Inst.dump());
llvm_unreachable("Unrecognized branch instruction");
}
return replaceBranchTarget(Inst, TBB, Ctx);
replaceBranchTarget(Inst, TBB, Ctx);
}
int getPCRelEncodingSize(const MCInst &Inst) const override {

7
bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
View File

@@ -151,14 +151,14 @@ public:
}
}
bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
void reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
auto Opcode = getInvertedBranchOpcode(Inst.getOpcode());
Inst.setOpcode(Opcode);
return replaceBranchTarget(Inst, TBB, Ctx);
replaceBranchTarget(Inst, TBB, Ctx);
}
bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
void replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) &&
"Invalid instruction");
@@ -170,7 +170,6 @@ public:
Inst.getOperand(SymOpIndex) = MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx));
return true;
}
IndirectBranchType analyzeIndirectBranch(

6
bolt/lib/Target/X86/X86MCPlusBuilder.cpp
View File

@@ -2794,14 +2794,13 @@ public:
Inst.addOperand(MCOperand::createImm(CC));
}
bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
void reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
unsigned InvCC = getInvertedCondCode(getCondCode(Inst));
assert(InvCC != X86::COND_INVALID && "invalid branch instruction");
Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(InvCC);
Inst.getOperand(0) = MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx));
return true;
}
bool replaceBranchCondition(MCInst &Inst, const MCSymbol *TBB, MCContext *Ctx,
@@ -2844,13 +2843,12 @@ public:
}
}
bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
void replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) &&
"Invalid instruction");
Inst.getOperand(0) = MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx));
return true;
}
MCPhysReg getX86R11() const override { return X86::R11; }