intel/llvm
1
0
Fork 0
mirror of https://github.com/intel/llvm.git synced 2026-01-31 16:29:50 +08:00
Code Issues Packages Projects Releases Wiki Activity

[AMDGPU] deduplicate tablegen predicates

Browse Source 
We are duplicating predicates if several parts of the combined
predicate list contain the same condition. Added code to deduplicate
the list.

We have AssemblerPredicates and AssemblerPredicate in the
PredicateControl, but we never use AssemblerPredicates with an
actual list, so this one is dropped.

This addresses the first part of the llvm bug 43886:
https://bugs.llvm.org/show_bug.cgi?id=43886

Differential Revision: https://reviews.llvm.org/D69815
This commit is contained in:
Stanislav Mekhanoshin
2019-11-04 11:50:18 -08:00
parent af11f417fc
commit 4312c4afd4
11 changed files with 46 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
View File

@@ -77,18 +77,26 @@ class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
def TruePredicate : Predicate<"">;
// Add a predicate to the list if does not already exist to deduplicate it.
class PredConcat<list<Predicate> lst, Predicate pred> {
list<Predicate> ret =
!foldl([pred], lst, acc, cur,
!listconcat(acc, !if(!eq(!cast<string>(cur),!cast<string>(pred)),
[], [cur])));
}
class PredicateControl {
Predicate SubtargetPredicate = TruePredicate;
list<Predicate> AssemblerPredicates = [];
Predicate AssemblerPredicate = TruePredicate;
Predicate WaveSizePredicate = TruePredicate;
list<Predicate> OtherPredicates = [];
list<Predicate> Predicates = !listconcat([SubtargetPredicate,
AssemblerPredicate,
WaveSizePredicate],
AssemblerPredicates,
OtherPredicates);
list<Predicate> Predicates = PredConcat<
PredConcat<PredConcat<OtherPredicates,
SubtargetPredicate>.ret,
AssemblerPredicate>.ret,
WaveSizePredicate>.ret;
}
class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
PredicateControl;

2
llvm/lib/Target/AMDGPU/DSInstructions.td
View File

@@ -1075,7 +1075,7 @@ defm DS_MAX_SRC2_F64 : DS_Real_gfx6_gfx7_gfx10<0x0d3>;
class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
DS_Real <ds>,
SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
let AssemblerPredicates = [isGFX8GFX9];
let AssemblerPredicate = isGFX8GFX9;
let DecoderNamespace = "GFX8";
// encoding

10
llvm/lib/Target/AMDGPU/MIMGInstructions.td
View File

@@ -183,7 +183,7 @@ class MIMGNSAHelper<int num_addrs> {
class MIMG_gfx6789<bits<8> op, dag outs, string dns = "">
: MIMG<outs, dns>, MIMGe_gfx6789<op> {
let SubtargetPredicate = isGFX6GFX7GFX8GFX9;
let AssemblerPredicates = [isGFX6GFX7GFX8GFX9];
let AssemblerPredicate = isGFX6GFX7GFX8GFX9;
let MIMGEncoding = MIMGEncGfx6;
@@ -194,7 +194,7 @@ class MIMG_gfx6789<bits<8> op, dag outs, string dns = "">
class MIMG_gfx10<int op, dag outs, string dns = "">
: MIMG<outs, dns>, MIMGe_gfx10<op> {
let SubtargetPredicate = isGFX10Plus;
let AssemblerPredicates = [isGFX10Plus];
let AssemblerPredicate = isGFX10Plus;
let MIMGEncoding = MIMGEncGfx10Default;
@@ -207,7 +207,7 @@ class MIMG_gfx10<int op, dag outs, string dns = "">
class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns="">
: MIMG<outs, dns>, MIMGe_gfx10<op> {
let SubtargetPredicate = isGFX10Plus;
let AssemblerPredicates = [isGFX10Plus];
let AssemblerPredicate = isGFX10Plus;
let MIMGEncoding = MIMGEncGfx10NSA;
@@ -416,13 +416,13 @@ class MIMG_Atomic_si<mimg op, string asm, RegisterClass data_rc,
RegisterClass addr_rc, bit enableDasm = 0>
: MIMG_Atomic_gfx6789_base<op.SI_GFX10, asm, data_rc, addr_rc,
!if(enableDasm, "GFX6GFX7", "")> {
let AssemblerPredicates = [isGFX6GFX7];
let AssemblerPredicate = isGFX6GFX7;
}
class MIMG_Atomic_vi<mimg op, string asm, RegisterClass data_rc,
RegisterClass addr_rc, bit enableDasm = 0>
: MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> {
let AssemblerPredicates = [isGFX8GFX9];
let AssemblerPredicate = isGFX8GFX9;
let MIMGEncoding = MIMGEncGfx8;
}

6
llvm/lib/Target/AMDGPU/SIInstrInfo.td
View File

@@ -1381,7 +1381,7 @@ multiclass EXP_m<bit done, SDPatternOperator node> {
def _si : EXP_Helper<done>,
SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.SI>,
EXPe {
let AssemblerPredicates = [isGFX6GFX7];
let AssemblerPredicate = isGFX6GFX7;
let DecoderNamespace = "GFX6GFX7";
let DisableDecoder = DisableSIDecoder;
}
@@ -1389,7 +1389,7 @@ multiclass EXP_m<bit done, SDPatternOperator node> {
def _vi : EXP_Helper<done>,
SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.VI>,
EXPe_vi {
let AssemblerPredicates = [isGFX8GFX9];
let AssemblerPredicate = isGFX8GFX9;
let DecoderNamespace = "GFX8";
let DisableDecoder = DisableVIDecoder;
}
@@ -1397,7 +1397,7 @@ multiclass EXP_m<bit done, SDPatternOperator node> {
def _gfx10 : EXP_Helper<done>,
SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.GFX10>,
EXPe {
let AssemblerPredicates = [isGFX10Plus];
let AssemblerPredicate = isGFX10Plus;
let DecoderNamespace = "GFX10";
let DisableDecoder = DisableSIDecoder;
}

10
llvm/lib/Target/AMDGPU/SMInstructions.td
View File

@@ -417,7 +417,7 @@ class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
, Enc32 {
let AssemblerPredicates = [isGFX6GFX7];
let AssemblerPredicate = isGFX6GFX7;
let DecoderNamespace = "GFX6GFX7";
let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
@@ -471,7 +471,7 @@ class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
, Enc64 {
bit glc;
let AssemblerPredicates = [isGFX8GFX9];
let AssemblerPredicate = isGFX8GFX9;
let DecoderNamespace = "GFX8";
let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
@@ -660,7 +660,7 @@ class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
SM_Real<ps>,
Enc64 {
let AssemblerPredicates = [isGFX7Only];
let AssemblerPredicate = isGFX7Only;
let DecoderNamespace = "GFX7";
let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc, DLC:$dlc);
@@ -697,7 +697,7 @@ class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
, Enc32 {
let AssemblerPredicates = [isGFX7Only];
let AssemblerPredicate = isGFX7Only;
let DecoderNamespace = "GFX7";
let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
@@ -835,7 +835,7 @@ class SMEM_Real_gfx10<bits<8> op, SM_Pseudo ps> :
bit glc;
bit dlc;
let AssemblerPredicates = [isGFX10Plus];
let AssemblerPredicate = isGFX10Plus;
let DecoderNamespace = "GFX10";
let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);

2
llvm/lib/Target/AMDGPU/SOPInstructions.td
View File

@@ -1503,7 +1503,7 @@ defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>;
class Select_vi<string opName> :
SIMCInstr<opName, SIEncodingFamily.VI> {
list<Predicate> AssemblerPredicates = [isGFX8GFX9];
Predicate AssemblerPredicate = isGFX8GFX9;
string DecoderNamespace = "GFX8";
}

6
llvm/lib/Target/AMDGPU/VOP1Instructions.td
View File

@@ -699,7 +699,7 @@ class VOP1_DPPe <bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
}
multiclass VOP1Only_Real_vi <bits<10> op> {
let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in {
let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
def _vi :
VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;
@@ -707,7 +707,7 @@ multiclass VOP1Only_Real_vi <bits<10> op> {
}
multiclass VOP1_Real_e32e64_vi <bits<10> op> {
let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in {
let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
def _e32_vi :
VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
@@ -899,7 +899,7 @@ def : GCNPat <
//===----------------------------------------------------------------------===//
multiclass VOP1_Real_gfx9 <bits<10> op> {
let AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" in {
let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
defm NAME : VOP1_Real_e32e64_vi <op>;
}

10
llvm/lib/Target/AMDGPU/VOP2Instructions.td
View File

@@ -1282,7 +1282,7 @@ defm V_MADAK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>;
// GFX8, GFX9 (VI).
//===----------------------------------------------------------------------===//
let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in {
let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
multiclass VOP2_Real_MADK_vi <bits<6> op> {
def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
@@ -1316,7 +1316,7 @@ multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
VOP2_Real_e32_vi<op>,
VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
} // End AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8"
} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
multiclass VOP2_SDWA_Real <bits<6> op> {
foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
@@ -1332,7 +1332,7 @@ multiclass VOP2_SDWA9_Real <bits<6> op> {
VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
}
let AssemblerPredicates = [isGFX8Only] in {
let AssemblerPredicate = isGFX8Only in {
multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
def _e32_vi :
@@ -1366,7 +1366,7 @@ multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName
}
}
let AssemblerPredicates = [isGFX9Only] in {
let AssemblerPredicate = isGFX9Only in {
multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
def _e32_gfx9 :
@@ -1424,7 +1424,7 @@ multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
}
}
} // AssemblerPredicates = [isGFX9Only]
} // AssemblerPredicate = isGFX9Only
multiclass VOP2_Real_e32e64_vi <bits<6> op> :
Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {

12
llvm/lib/Target/AMDGPU/VOP3Instructions.td
View File

@@ -927,7 +927,7 @@ defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>;
// GFX8, GFX9 (VI).
//===----------------------------------------------------------------------===//
let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in {
let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
multiclass VOP3_Real_vi<bits<10> op> {
def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
@@ -949,9 +949,9 @@ multiclass VOP3Interp_Real_vi<bits<10> op> {
VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>;
}
} // End AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8"
} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
let AssemblerPredicates = [isGFX8Only], DecoderNamespace = "GFX8" in {
let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in {
multiclass VOP3_F16_Real_vi<bits<10> op> {
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
@@ -963,9 +963,9 @@ multiclass VOP3Interp_F16_Real_vi<bits<10> op> {
VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
}
} // End AssemblerPredicates = [isGFX8Only], DecoderNamespace = "GFX8"
} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8"
let AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" in {
let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
@@ -999,7 +999,7 @@ multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
}
}
} // End AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9"
} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9"
defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>;

4
llvm/lib/Target/AMDGPU/VOP3PInstructions.td
View File

@@ -404,7 +404,7 @@ def : MnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">;
multiclass VOP3P_Real_vi<bits<10> op> {
def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
VOP3Pe <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
let AssemblerPredicates = [HasVOP3PInsts];
let AssemblerPredicate = HasVOP3PInsts;
let DecoderNamespace = "GFX8";
}
}
@@ -412,7 +412,7 @@ multiclass VOP3P_Real_vi<bits<10> op> {
multiclass VOP3P_Real_MAI<bits<10> op> {
def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
VOP3Pe_MAI <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
let AssemblerPredicates = [HasMAIInsts];
let AssemblerPredicate = HasMAIInsts;
let DecoderNamespace = "GFX8";
}
}

2
llvm/lib/Target/AMDGPU/VOPCInstructions.td
View File

@@ -1218,7 +1218,7 @@ defm V_CMPX_T_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f7>;
//===----------------------------------------------------------------------===//
multiclass VOPC_Real_vi <bits<10> op> {
let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in {
let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
def _e32_vi :
VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
VOPCe<op{7-0}>;