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https://github.com/intel/llvm.git
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[PowerPC][NFC] Refactor PPCInstrFutureMMA.td to combine sections (#151194)
Combine same predicate sections into one and move some mma instructions into the proper section.
This commit is contained in:
Lei Huang
GitHub
@@ -8,6 +8,7 @@
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions introduced for the Future CPU for MMA.
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// Please reference "PPCInstrVSX.td" for file structure.
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//
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//===----------------------------------------------------------------------===//
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@@ -390,7 +391,12 @@ class XX2Form_AT3_XB6_ID2_E1_BL2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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let Inst{31} = 0;
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}
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let Predicates = [IsISAFuture] in {
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//-------------------------- Instruction definitions -------------------------//
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// Predicate combinations available:
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// [MMA, IsISAFuture]
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// [MMA, PrefixInstrs, IsISAFuture]
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let Predicates = [MMA, IsISAFuture] in {
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def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
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(outs vsrprc:$XAp, vsrprc:$XBp),
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(ins wacc:$AT),
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@@ -437,188 +443,187 @@ let Predicates = [IsISAFuture] in {
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def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins),
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"dmsetdmrz $AT", NoItinerary,
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[(set v1024i1:$AT, (int_ppc_mma_dmsetdmrz))]>;
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}
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// MMA+ accumulating/non-accumulating instructions.
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// DMXVI8GERX4, DMXVI8GERX4PP, PMDMXVI8GERX4, PMDMXVI8GERX4PP
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defm DMXVI8GERX4 : DMR_UM_M448_XOEO<59, 10, (ins vsrprc:$XAp, vsrc:$XB),
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"dmxvi8gerx4", "$AT, $XAp, $XB">;
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// DMXVI8GERX4, DMXVI8GERX4PP, PMDMXVI8GERX4, PMDMXVI8GERX4PP
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defm DMXVI8GERX4 : DMR_UM_M448_XOEO<59, 10, (ins vsrprc:$XAp, vsrc:$XB),
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"dmxvi8gerx4", "$AT, $XAp, $XB">;
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// DMXVBF16GERX2, DMXVBF16GERX2PP, DMXVBF16GERX2PN, dMXVBF16GERX2NP,
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// DMXVBF16GERX2NN PMDMXVBF16GERX2, PMDMXVBF16GERX2PP, PMDMXVBF16GERX2PN,
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// PMDMXVBF16GERX2NP, PMDMXVBF16GERX2NN
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defm DMXVBF16GERX2
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: DMR_NEG_UM_M284_XOXORf939a0<59, 74, (ins vsrprc:$XAp, vsrc:$XB),
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"dmxvbf16gerx2", "$AT, $XAp, $XB">;
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let Predicates = [MMA, IsISAFuture] in {
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def DMXVI8GERX4SPP :
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XX3Form_AT3_XAp5B6<59, 98, (outs dmr:$AT), (ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB),
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"dmxvi8gerx4spp $AT, $XAp, $XB", IIC_VecGeneral, []>,
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RegConstraint<"$ATi = $AT">;
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}
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// DMXVF16GERX2, DMXVF16GERX2PP, DMXVF16GERX2PN, dMXVF16GERX2NP,
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// DMXVF16GERX2NN PMDMXVF16GERX2, PMDMXVF16GERX2PP, PMDMXVF16GERX2PN,
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// PMDMXVF16GERX2NP, PMDMXVF16GERX2NN
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defm DMXVF16GERX2
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: DMR_NEG_UM_M284_XOXORd11188<59, 66, (ins vsrprc:$XAp, vsrc:$XB),
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"dmxvf16gerx2", "$AT, $XAp, $XB">;
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// DMF cryptography [support] Instructions
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def DMSHA2HASH
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: XForm_AT3_T1_AB3<
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31, 14, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB, u1imm:$T),
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"dmsha2hash $AT, $AB, $T",
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[(set v1024i1:$AT, (int_ppc_mma_dmsha2hash v1024i1:$ATi,
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v1024i1:$AB, timm:$T))]>,
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RegConstraint<"$ATi = $AT">;
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def DMSHA3HASH
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: XForm_ATp2_SR5<31, 15, 177, (outs dmrp:$ATp),
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(ins dmrp:$ATpi, u5imm:$SR), "dmsha3hash $ATp, $SR",
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[(set v2048i1:$ATp,
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(int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>,
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RegConstraint<"$ATpi = $ATp">;
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def DMXXSHAPAD
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: XX2Form_AT3_XB6_ID2_E1_BL2<60, 421, (outs dmr:$AT),
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(ins dmr:$ATi, vsrc:$XB, u2imm:$ID, u1imm:$E,
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u2imm:$BL),
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"dmxxshapad $AT, $XB, $ID, $E, $BL", []>,
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RegConstraint<"$ATi = $AT">;
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// MMA+ accumulating/non-accumulating instructions.
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def DMXVI8GERX4SPP
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: XX3Form_AT3_XAp5B6<59, 98, (outs dmr:$AT),
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(ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB),
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"dmxvi8gerx4spp $AT, $XAp, $XB", IIC_VecGeneral, []>,
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RegConstraint<"$ATi = $AT">;
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} // End of [MMA, IsISAFuture]
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let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
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def PMDMXVI8GERX4SPP :
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MMIRR_XX3Form_X8YP4_XAp5B6<59, 98, (outs dmr:$AT),
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(ins dmr:$ATi, vsrprc:$XAp,vsrc:$XB, u8imm:$XMSK,
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u4imm:$YMSK, u4imm:$PMSK),
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"pmdmxvi8gerx4spp $AT, $XAp, $XB, $XMSK, $YMSK, $PMSK",
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IIC_VecGeneral, []>,
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RegConstraint<"$ATi = $AT">;
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def PMDMXVI8GERX4SPP
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: MMIRR_XX3Form_X8YP4_XAp5B6<
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59, 98, (outs dmr:$AT),
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(ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB, u8imm:$XMSK, u4imm:$YMSK,
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u4imm:$PMSK),
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"pmdmxvi8gerx4spp $AT, $XAp, $XB, $XMSK, $YMSK, $PMSK",
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IIC_VecGeneral, []>,
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RegConstraint<"$ATi = $AT">;
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}
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// DMXVBF16GERX2, DMXVBF16GERX2PP, DMXVBF16GERX2PN, dMXVBF16GERX2NP, DMXVBF16GERX2NN
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// PMDMXVBF16GERX2, PMDMXVBF16GERX2PP, PMDMXVBF16GERX2PN, PMDMXVBF16GERX2NP, PMDMXVBF16GERX2NN
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defm DMXVBF16GERX2 : DMR_NEG_UM_M284_XOXORf939a0<59, 74, (ins vsrprc:$XAp, vsrc:$XB),
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"dmxvbf16gerx2", "$AT, $XAp, $XB">;
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//---------------------------- Anonymous Patterns ----------------------------//
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// Predicate combinations available:
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// [MMA, IsISAFuture]
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// [MMA, PrefixInstrs, IsISAFuture]
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// DMXVF16GERX2, DMXVF16GERX2PP, DMXVF16GERX2PN, dMXVF16GERX2NP, DMXVF16GERX2NN
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// PMDMXVF16GERX2, PMDMXVF16GERX2PP, PMDMXVF16GERX2PN, PMDMXVF16GERX2NP, PMDMXVF16GERX2NN
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defm DMXVF16GERX2 : DMR_NEG_UM_M284_XOXORd11188<59, 66, (ins vsrprc:$XAp, vsrc:$XB),
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"dmxvf16gerx2", "$AT, $XAp, $XB">;
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// DMF cryptography [support] Instructions
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let Predicates = [IsISAFuture] in {
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def DMSHA2HASH :
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XForm_AT3_T1_AB3<31, 14, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB, u1imm:$T),
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"dmsha2hash $AT, $AB, $T",
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[(set v1024i1:$AT, (int_ppc_mma_dmsha2hash v1024i1:$ATi, v1024i1:$AB, timm:$T))]>,
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RegConstraint<"$ATi = $AT">;
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def DMSHA3HASH :
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XForm_ATp2_SR5<31, 15, 177, (outs dmrp:$ATp), (ins dmrp:$ATpi , u5imm:$SR),
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"dmsha3hash $ATp, $SR",
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[(set v2048i1:$ATp, (int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>,
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RegConstraint<"$ATpi = $ATp">;
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def DMXXSHAPAD :
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XX2Form_AT3_XB6_ID2_E1_BL2<60, 421, (outs dmr:$AT),
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(ins dmr:$ATi, vsrc:$XB, u2imm:$ID, u1imm:$E, u2imm:$BL),
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"dmxxshapad $AT, $XB, $ID, $E, $BL", []>,
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RegConstraint<"$ATi = $AT">;
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}
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// MMA+ Intrinsics
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let Predicates = [MMA, IsISAFuture] in {
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def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4 v256i1:$XAp, v16i8:$XB)),
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// MMA+ Intrinsics
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def : Pat<(v1024i1(int_ppc_mma_dmxvi8gerx4 v256i1:$XAp, v16i8:$XB)),
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(DMXVI8GERX4 $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB)),
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(DMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB)),
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(DMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2 v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvbf16gerx2 v256i1:$XAp, v16i8:$XB)),
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(DMXVBF16GERX2 $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB)),
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(DMXVBF16GERX2PP $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB)),
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(DMXVBF16GERX2PN $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB)),
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(DMXVBF16GERX2NP $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB)),
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(DMXVBF16GERX2NN $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2 v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvf16gerx2 v256i1:$XAp, v16i8:$XB)),
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(DMXVF16GERX2 $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB)),
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(DMXVF16GERX2PP $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB)),
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(DMXVF16GERX2PN $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB)),
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(DMXVF16GERX2NP $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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def : Pat<(v1024i1(int_ppc_mma_dmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB)),
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(DMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC)>;
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// Cryptography Intrinsic
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def : Pat<(v1024i1(int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB, timm:$ID,
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timm:$E, timm:$BL)),
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(DMXXSHAPAD $ATi, RCCp.BToVSRC, $ID, $E, $BL)>;
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}
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let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
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(PMDMXVI8GERX4 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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def : Pat<(v1024i1(int_ppc_mma_pmdmxvi8gerx4 v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
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(PMDMXVI8GERX4 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk4Imm:$PMSK)>;
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk4Imm:$PMSK)),
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def : Pat<(v1024i1(int_ppc_mma_pmdmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
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(PMDMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk4Imm:$PMSK)),
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def : Pat<(v1024i1(int_ppc_mma_pmdmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
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(PMDMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
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(PMDMXVBF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
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def : Pat<(v1024i1(int_ppc_mma_pmdmxvbf16gerx2 v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
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(PMDMXVBF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk2Imm:$PMSK)>;
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk2Imm:$PMSK)),
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def : Pat<(v1024i1(int_ppc_mma_pmdmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
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(PMDMXVBF16GERX2PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
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Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk2Imm:$PMSK)),
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def : Pat<(v1024i1(int_ppc_mma_pmdmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
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(PMDMXVBF16GERX2PN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
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Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk2Imm:$PMSK)),
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def : Pat<(v1024i1(int_ppc_mma_pmdmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp,
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v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
|
||||
(PMDMXVBF16GERX2NP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
|
||||
def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
|
||||
Msk8Imm:$XMSK, Msk4Imm:$YMSK,
|
||||
Msk2Imm:$PMSK)),
|
||||
def : Pat<(v1024i1(int_ppc_mma_pmdmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
|
||||
v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
|
||||
(PMDMXVBF16GERX2NN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
|
||||
def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
|
||||
(PMDMXVF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
def : Pat<(v1024i1(int_ppc_mma_pmdmxvf16gerx2 v256i1:$XAp, v16i8:$XB,
|
||||
Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
|
||||
(PMDMXVF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, Msk4Imm:$YMSK,
|
||||
Msk2Imm:$PMSK)>;
|
||||
|
||||
def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
|
||||
Msk8Imm:$XMSK, Msk4Imm:$YMSK,
|
||||
Msk2Imm:$PMSK)),
|
||||
def : Pat<(v1024i1(int_ppc_mma_pmdmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
|
||||
v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
|
||||
(PMDMXVF16GERX2PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
|
||||
def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
|
||||
Msk8Imm:$XMSK, Msk4Imm:$YMSK,
|
||||
Msk2Imm:$PMSK)),
|
||||
def : Pat<(v1024i1(int_ppc_mma_pmdmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
|
||||
v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
|
||||
(PMDMXVF16GERX2PN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
|
||||
def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
|
||||
Msk8Imm:$XMSK, Msk4Imm:$YMSK,
|
||||
Msk2Imm:$PMSK)),
|
||||
def : Pat<(v1024i1(int_ppc_mma_pmdmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp,
|
||||
v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
|
||||
(PMDMXVF16GERX2NP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
|
||||
def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
|
||||
Msk8Imm:$XMSK, Msk4Imm:$YMSK,
|
||||
Msk2Imm:$PMSK)),
|
||||
def : Pat<(v1024i1(int_ppc_mma_pmdmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
|
||||
v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
|
||||
(PMDMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
|
||||
}
|
||||
|
||||
// Cryptography Intrinsic
|
||||
let Predicates = [IsISAFuture] in {
|
||||
def : Pat<(v1024i1 (int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB, timm:$ID,
|
||||
timm:$E, timm:$BL)), (DMXXSHAPAD $ATi, RCCp.BToVSRC, $ID, $E, $BL)>;
|
||||
}
|
||||
|
||||
// MMA+ Instruction aliases
|
||||
let Predicates = [IsISAFuture] in {
|
||||
//---------------------------- Instruction aliases ---------------------------//
|
||||
|
||||
let Predicates = [MMA, IsISAFuture] in {
|
||||
def : InstAlias<"dmsha256hash $AT, $AB",
|
||||
(DMSHA2HASH dmr:$AT, dmr:$AB, 0)>;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user