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[RISCV] Use implicit def/use of SP for PROBED_STACKALLOC*. (#139153)
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@@ -633,7 +633,6 @@ void RISCVFrameLowering::allocateAndProbeStackForRVV(
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// It will be expanded to a probe loop in `inlineStackProbe`.
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::PROBED_STACKALLOC_RVV))
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.addReg(SPReg)
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.addReg(TargetReg);
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if (EmitCFI) {
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@@ -828,9 +827,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB,
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}
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// It will be expanded to a probe loop in `inlineStackProbe`.
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::PROBED_STACKALLOC))
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.addReg(SPReg)
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.addReg(TargetReg);
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::PROBED_STACKALLOC)).addReg(TargetReg);
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if (EmitCFI) {
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// Set the CFA register back to SP.
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@@ -2433,7 +2430,7 @@ void RISCVFrameLowering::inlineStackProbe(MachineFunction &MF,
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MI->getOpcode() == RISCV::PROBED_STACKALLOC_RVV) {
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MachineBasicBlock::iterator MBBI = MI->getIterator();
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DebugLoc DL = MBB.findDebugLoc(MBBI);
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Register TargetReg = MI->getOperand(1).getReg();
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Register TargetReg = MI->getOperand(0).getReg();
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emitStackProbeInline(MBBI, DL, TargetReg,
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(MI->getOpcode() == RISCV::PROBED_STACKALLOC_RVV));
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MBBI->eraseFromParent();
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@@ -1518,17 +1518,18 @@ def GIAddrRegImm :
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/// Stack probing
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let hasSideEffects = 1, mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
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let hasSideEffects = 1, mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
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Defs = [X2], Uses = [X2] in {
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// Probed stack allocation of a constant size, used in function prologues when
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// stack-clash protection is enabled.
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def PROBED_STACKALLOC : Pseudo<(outs GPR:$sp),
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(ins GPR:$target),
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[]>,
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Sched<[]>;
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def PROBED_STACKALLOC_RVV : Pseudo<(outs GPR:$sp),
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def PROBED_STACKALLOC : Pseudo<(outs),
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(ins GPR:$target),
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[]>,
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Sched<[]>;
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def PROBED_STACKALLOC_RVV : Pseudo<(outs),
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(ins GPR:$target),
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[]>,
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Sched<[]>;
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let usesCustomInserter = 1 in
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def PROBED_STACKALLOC_DYN : Pseudo<(outs),
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(ins GPR:$target),
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