[LLDB][RISCV] Fix risc-v target build

Fixed an inconsistency between D130985 and D130342

This should be a follow-up of D130985

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D131667

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp

@@ -10,6 +10,7 @@
 
 #include "NativeRegisterContextLinux_riscv64.h"
 
+#include "lldb/Host/HostInfo.h"
 #include "lldb/Utility/DataBufferHeap.h"
 #include "lldb/Utility/Log.h"
 #include "lldb/Utility/RegisterValue.h"
@@ -48,6 +49,11 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
   }
 }
 
+llvm::Expected<ArchSpec>
+NativeRegisterContextLinux::DetermineArchitecture(lldb::tid_t tid) {
+  return HostInfo::GetArchitecture();
+}
+
 NativeRegisterContextLinux_riscv64::NativeRegisterContextLinux_riscv64(
     const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
     std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up)

lldb/source/Utility/RISCV_DWARF_Registers.h

@@ -124,7 +124,7 @@ enum {
   dwarf_gpr_fp = dwarf_gpr_x8,
 
   // mock pc regnum
-  dwarf_gpr_pc = UINT32_MAX,
+  dwarf_gpr_pc = 11451,
 };
 
 } // namespace riscv_dwarf