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[FastISel] Use Register. NFC

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This focuses on the common interfaces and tablegen. More changes
are needed to individual targets.
This commit is contained in:
Craig Topper
2025-03-05 09:13:02 -08:00
parent 39c454af01
commit 58670aa79a
9 changed files with 112 additions and 101 deletions
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24
llvm/include/llvm/CodeGen/FastISel.h
View File

@@ -348,21 +348,21 @@ protected:
/// This method is called by target-independent code to request that an
/// instruction with the given type and opcode be emitted.
virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
virtual Register fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
/// This method is called by target-independent code to request that an
/// instruction with the given type, opcode, and register operand be emitted.
virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0);
virtual Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0);
/// This method is called by target-independent code to request that an
/// instruction with the given type, opcode, and register operands be emitted.
virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
virtual Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
Register Op1);
/// This method is called by target-independent code to request that an
/// instruction with the given type, opcode, and register and immediate
/// operands be emitted.
virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
virtual Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
uint64_t Imm);
/// This method is a wrapper of fastEmit_ri.
@@ -375,12 +375,12 @@ protected:
/// This method is called by target-independent code to request that an
/// instruction with the given type, opcode, and immediate operand be emitted.
virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
virtual Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
/// This method is called by target-independent code to request that an
/// instruction with the given type, opcode, and floating-point immediate
/// operand be emitted.
virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
virtual Register fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
const ConstantFP *FPImm);
/// Emit a MachineInstr with no operands and a result register in the
@@ -470,15 +470,19 @@ protected:
/// Emit a constant in a register using target-specific logic, such as
/// constant pool loads.
virtual unsigned fastMaterializeConstant(const Constant *C) { return 0; }
virtual Register fastMaterializeConstant(const Constant *C) {
return Register();
}
/// Emit an alloca address in a register using target-specific logic.
virtual unsigned fastMaterializeAlloca(const AllocaInst *C) { return 0; }
virtual Register fastMaterializeAlloca(const AllocaInst *C) {
return Register();
}
/// Emit the floating-point constant +0.0 in a register using target-
/// specific logic.
virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF) {
return 0;
virtual Register fastMaterializeFloatZero(const ConstantFP *CF) {
return Register();
}
/// Check if \c Add is an add that can be safely folded into \c GEP.

31
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@@ -156,7 +156,8 @@ bool FastISel::lowerArguments() {
}
/// Return the defined register if this instruction defines exactly one
/// virtual register and uses no other virtual registers. Otherwise return 0.
/// virtual register and uses no other virtual registers. Otherwise return
/// Register();
static Register findLocalRegDef(MachineInstr &MI) {
Register RegDef;
for (const MachineOperand &MO : MI.operands()) {
@@ -315,7 +316,7 @@ Register FastISel::materializeConstant(const Value *V, MVT VT) {
if (!selectOperator(Op, Op->getOpcode()))
if (!isa<Instruction>(Op) ||
!fastSelectInstruction(cast<Instruction>(Op)))
return 0;
return Register();
Reg = lookUpRegForValue(Op);
} else if (isa<UndefValue>(V)) {
Reg = createResultReg(TLI.getRegClassFor(VT));
@@ -1950,29 +1951,29 @@ bool FastISel::fastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
return false;
}
unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
Register FastISel::fastEmit_(MVT, MVT, unsigned) { return Register(); }
unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, Register /*Op0*/) {
return 0;
Register FastISel::fastEmit_r(MVT, MVT, unsigned, Register /*Op0*/) {
return Register();
}
unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, Register /*Op0*/,
Register FastISel::fastEmit_rr(MVT, MVT, unsigned, Register /*Op0*/,
Register /*Op1*/) {
return 0;
return Register();
}
unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
return 0;
Register FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
return Register();
}
unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
Register FastISel::fastEmit_f(MVT, MVT, unsigned,
const ConstantFP * /*FPImm*/) {
return 0;
return Register();
}
unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, Register /*Op0*/,
Register FastISel::fastEmit_ri(MVT, MVT, unsigned, Register /*Op0*/,
uint64_t /*Imm*/) {
return 0;
return Register();
}
/// This method is a wrapper of fastEmit_ri. It first tries to emit an
@@ -1995,7 +1996,7 @@ Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, Register Op0,
// in-range.
if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
Imm >= VT.getSizeInBits())
return 0;
return Register();
// First check if immediate type is legal. If not, we can't use the ri form.
Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Imm);
@@ -2009,7 +2010,7 @@ Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, Register Op0,
IntegerType::get(FuncInfo.Fn->getContext(), VT.getSizeInBits());
MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
if (!MaterialReg)
return 0;
return Register();
}
return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
}

24
llvm/lib/Target/AArch64/AArch64FastISel.cpp
View File

@@ -277,9 +277,9 @@ private:
public:
// Backend specific FastISel code.
unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
unsigned fastMaterializeConstant(const Constant *C) override;
unsigned fastMaterializeFloatZero(const ConstantFP* CF) override;
Register fastMaterializeAlloca(const AllocaInst *AI) override;
Register fastMaterializeConstant(const Constant *C) override;
Register fastMaterializeFloatZero(const ConstantFP *CF) override;
explicit AArch64FastISel(FunctionLoweringInfo &FuncInfo,
const TargetLibraryInfo *LibInfo)
@@ -346,13 +346,13 @@ CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
return CC_AArch64_AAPCS;
}
unsigned AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
Register AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i64 &&
"Alloca should always return a pointer.");
// Don't handle dynamic allocas.
if (!FuncInfo.StaticAllocaMap.count(AI))
return 0;
return Register();
DenseMap<const AllocaInst *, int>::iterator SI =
FuncInfo.StaticAllocaMap.find(AI);
@@ -367,7 +367,7 @@ unsigned AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
return ResultReg;
}
return 0;
return Register();
}
unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) {
@@ -537,12 +537,12 @@ unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {
return ResultReg;
}
unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) {
Register AArch64FastISel::fastMaterializeConstant(const Constant *C) {
EVT CEVT = TLI.getValueType(DL, C->getType(), true);
// Only handle simple types.
if (!CEVT.isSimple())
return 0;
return Register();
MVT VT = CEVT.getSimpleVT();
// arm64_32 has 32-bit pointers held in 64-bit registers. Because of that,
// 'null' pointers need to have a somewhat special treatment.
@@ -558,18 +558,18 @@ unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) {
else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
return materializeGV(GV);
return 0;
return Register();
}
unsigned AArch64FastISel::fastMaterializeFloatZero(const ConstantFP* CFP) {
Register AArch64FastISel::fastMaterializeFloatZero(const ConstantFP *CFP) {
assert(CFP->isNullValue() &&
"Floating-point constant is not a positive zero.");
MVT VT;
if (!isTypeLegal(CFP->getType(), VT))
return 0;
return Register();
if (VT != MVT::f32 && VT != MVT::f64)
return 0;
return Register();
bool Is64Bit = (VT == MVT::f64);
unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;

21
llvm/lib/Target/ARM/ARMFastISel.cpp
View File

@@ -147,8 +147,8 @@ class ARMFastISel final : public FastISel {
// Backend specific FastISel code.
bool fastSelectInstruction(const Instruction *I) override;
unsigned fastMaterializeConstant(const Constant *C) override;
unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
Register fastMaterializeConstant(const Constant *C) override;
Register fastMaterializeAlloca(const AllocaInst *AI) override;
bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
const LoadInst *LI) override;
bool fastLowerArguments() override;
@@ -619,11 +619,12 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
return DestReg;
}
unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
Register ARMFastISel::fastMaterializeConstant(const Constant *C) {
EVT CEVT = TLI.getValueType(DL, C->getType(), true);
// Only handle simple types.
if (!CEVT.isSimple()) return 0;
if (!CEVT.isSimple())
return Register();
MVT VT = CEVT.getSimpleVT();
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
@@ -633,17 +634,19 @@ unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
else if (isa<ConstantInt>(C))
return ARMMaterializeInt(C, VT);
return 0;
return Register();
}
// TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
Register ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
// Don't handle dynamic allocas.
if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
if (!FuncInfo.StaticAllocaMap.count(AI))
return Register();
MVT VT;
if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
if (!isLoadTypeLegal(AI->getType(), VT))
return Register();
DenseMap<const AllocaInst*, int>::iterator SI =
FuncInfo.StaticAllocaMap.find(AI);
@@ -663,7 +666,7 @@ unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
return ResultReg;
}
return 0;
return Register();
}
bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {

14
llvm/lib/Target/Mips/MipsFastISel.cpp
View File

@@ -255,8 +255,8 @@ public:
UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
}
unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
unsigned fastMaterializeConstant(const Constant *C) override;
Register fastMaterializeAlloca(const AllocaInst *AI) override;
Register fastMaterializeConstant(const Constant *C) override;
bool fastSelectInstruction(const Instruction *I) override;
#include "MipsGenFastISel.inc"
@@ -327,7 +327,7 @@ unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
return ResultReg;
}
unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
Register MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
"Alloca should always return a pointer.");
@@ -343,7 +343,7 @@ unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
return ResultReg;
}
return 0;
return Register();
}
unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
@@ -437,12 +437,12 @@ unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
// Materialize a constant into a register, and return the register
// number (or zero if we failed to handle it).
unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
Register MipsFastISel::fastMaterializeConstant(const Constant *C) {
EVT CEVT = TLI.getValueType(DL, C->getType(), true);
// Only handle simple types.
if (!CEVT.isSimple())
return 0;
return Register();
MVT VT = CEVT.getSimpleVT();
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
@@ -452,7 +452,7 @@ unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
else if (isa<ConstantInt>(C))
return materializeInt(C, VT);
return 0;
return Register();
}
bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {

29
llvm/lib/Target/PowerPC/PPCFastISel.cpp
View File

@@ -98,12 +98,12 @@ class PPCFastISel final : public FastISel {
// Backend specific FastISel code.
private:
bool fastSelectInstruction(const Instruction *I) override;
unsigned fastMaterializeConstant(const Constant *C) override;
unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
Register fastMaterializeConstant(const Constant *C) override;
Register fastMaterializeAlloca(const AllocaInst *AI) override;
bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
const LoadInst *LI) override;
bool fastLowerArguments() override;
unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
Register fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, uint64_t Imm);
@@ -2242,11 +2242,12 @@ unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
// Materialize a constant into a register, and return the register
// number (or zero if we failed to handle it).
unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
Register PPCFastISel::fastMaterializeConstant(const Constant *C) {
EVT CEVT = TLI.getValueType(DL, C->getType(), true);
// Only handle simple types.
if (!CEVT.isSimple()) return 0;
if (!CEVT.isSimple())
return Register();
MVT VT = CEVT.getSimpleVT();
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
@@ -2261,17 +2262,19 @@ unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
// instruction selection.
return PPCMaterializeInt(CI, VT, false);
return 0;
return Register();
}
// Materialize the address created by an alloca into a register, and
// return the register number (or zero if we failed to handle it).
unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
Register PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
// Don't handle dynamic allocas.
if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
if (!FuncInfo.StaticAllocaMap.count(AI))
return Register();
MVT VT;
if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
if (!isLoadTypeLegal(AI->getType(), VT))
return Register();
DenseMap<const AllocaInst*, int>::iterator SI =
FuncInfo.StaticAllocaMap.find(AI);
@@ -2283,7 +2286,7 @@ unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
return ResultReg;
}
return 0;
return Register();
}
// Fold loads into extends when possible.
@@ -2379,10 +2382,10 @@ bool PPCFastISel::fastLowerArguments() {
// Handle materializing integer constants into a register. This is not
// automatically generated for PowerPC, so must be explicitly created here.
unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
Register PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
if (Opc != ISD::Constant)
return 0;
return Register();
// If we're using CR bit registers for i1 values, handle that as a special
// case first.
@@ -2395,7 +2398,7 @@ unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
VT != MVT::i1)
return 0;
return Register();
const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
&PPC::GPRCRegClass);

16
llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
View File

@@ -174,8 +174,8 @@ private:
unsigned copyValue(unsigned Reg);
// Backend specific FastISel code.
unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
unsigned fastMaterializeConstant(const Constant *C) override;
Register fastMaterializeAlloca(const AllocaInst *AI) override;
Register fastMaterializeConstant(const Constant *C) override;
bool fastLowerArguments() override;
// Selection routines.
@@ -610,7 +610,7 @@ unsigned WebAssemblyFastISel::copyValue(unsigned Reg) {
return ResultReg;
}
unsigned WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
Register WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
DenseMap<const AllocaInst *, int>::iterator SI =
FuncInfo.StaticAllocaMap.find(AI);
@@ -625,15 +625,15 @@ unsigned WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
return ResultReg;
}
return 0;
return Register();
}
unsigned WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
Register WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
if (TLI.isPositionIndependent())
return 0;
return Register();
if (GV->isThreadLocal())
return 0;
return Register();
Register ResultReg =
createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
: &WebAssembly::I32RegClass);
@@ -645,7 +645,7 @@ unsigned WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
}
// Let target-independent code handle it.
return 0;
return Register();
}
bool WebAssemblyFastISel::fastLowerArguments() {

32
llvm/lib/Target/X86/X86FastISel.cpp
View File

@@ -137,11 +137,11 @@ private:
unsigned X86MaterializeInt(const ConstantInt *CI, MVT VT);
unsigned X86MaterializeFP(const ConstantFP *CFP, MVT VT);
unsigned X86MaterializeGV(const GlobalValue *GV, MVT VT);
unsigned fastMaterializeConstant(const Constant *C) override;
Register fastMaterializeConstant(const Constant *C) override;
unsigned fastMaterializeAlloca(const AllocaInst *C) override;
Register fastMaterializeAlloca(const AllocaInst *C) override;
unsigned fastMaterializeFloatZero(const ConstantFP *CF) override;
Register fastMaterializeFloatZero(const ConstantFP *CF) override;
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
/// computed in an SSE register, not on the X87 floating point stack.
@@ -3778,7 +3778,7 @@ unsigned X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) {
CodeModel::Model CM = TM.getCodeModel();
if (CM != CodeModel::Small && CM != CodeModel::Medium &&
CM != CodeModel::Large)
return 0;
return Register();
// Get opcode and regclass of the output for the given load instruction.
unsigned Opc = 0;
@@ -3787,7 +3787,8 @@ unsigned X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) {
bool HasAVX = Subtarget->hasAVX();
bool HasAVX512 = Subtarget->hasAVX512();
switch (VT.SimpleTy) {
default: return 0;
default:
return Register();
case MVT::f32:
Opc = HasAVX512 ? X86::VMOVSSZrm_alt
: HasAVX ? X86::VMOVSSrm_alt
@@ -3802,7 +3803,7 @@ unsigned X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) {
break;
case MVT::f80:
// No f80 support yet.
return 0;
return Register();
}
// MachineConstantPool wants an explicit alignment.
@@ -3883,12 +3884,12 @@ unsigned X86FastISel::X86MaterializeGV(const GlobalValue *GV, MVT VT) {
return 0;
}
unsigned X86FastISel::fastMaterializeConstant(const Constant *C) {
Register X86FastISel::fastMaterializeConstant(const Constant *C) {
EVT CEVT = TLI.getValueType(DL, C->getType(), true);
// Only handle simple types.
if (!CEVT.isSimple())
return 0;
return Register();
MVT VT = CEVT.getSimpleVT();
if (const auto *CI = dyn_cast<ConstantInt>(C))
@@ -3923,10 +3924,10 @@ unsigned X86FastISel::fastMaterializeConstant(const Constant *C) {
}
}
return 0;
return Register();
}
unsigned X86FastISel::fastMaterializeAlloca(const AllocaInst *C) {
Register X86FastISel::fastMaterializeAlloca(const AllocaInst *C) {
// Fail on dynamic allocas. At this point, getRegForValue has already
// checked its CSE maps, so if we're here trying to handle a dynamic
// alloca, we're not going to succeed. X86SelectAddress has a
@@ -3935,12 +3936,12 @@ unsigned X86FastISel::fastMaterializeAlloca(const AllocaInst *C) {
// in order to avoid recursion between getRegForValue,
// X86SelectAddrss, and targetMaterializeAlloca.
if (!FuncInfo.StaticAllocaMap.count(C))
return 0;
return Register();
assert(C->isStaticAlloca() && "dynamic alloca in the static alloca map?");
X86AddressMode AM;
if (!X86SelectAddress(C, AM))
return 0;
return Register();
unsigned Opc =
TLI.getPointerTy(DL) == MVT::i32
? (Subtarget->isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r)
@@ -3952,10 +3953,10 @@ unsigned X86FastISel::fastMaterializeAlloca(const AllocaInst *C) {
return ResultReg;
}
unsigned X86FastISel::fastMaterializeFloatZero(const ConstantFP *CF) {
Register X86FastISel::fastMaterializeFloatZero(const ConstantFP *CF) {
MVT VT;
if (!isTypeLegal(CF->getType(), VT))
return 0;
return Register();
// Get opcode and regclass for the given zero.
bool HasSSE1 = Subtarget->hasSSE1();
@@ -3979,7 +3980,7 @@ unsigned X86FastISel::fastMaterializeFloatZero(const ConstantFP *CF) {
break;
case MVT::f80:
// No f80 support yet.
return 0;
return Register();
}
Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
@@ -3987,7 +3988,6 @@ unsigned X86FastISel::fastMaterializeFloatZero(const ConstantFP *CF) {
return ResultReg;
}
bool X86FastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
const LoadInst *LI) {
const Value *Ptr = LI->getPointerOperand();

22
llvm/utils/TableGen/FastISelEmitter.cpp
View File

@@ -684,10 +684,10 @@ void FastISelMap::emitInstructionCode(raw_ostream &OS,
OS << " }\n";
}
}
// Return 0 if all of the possibilities had predicates but none
// Return Register() if all of the possibilities had predicates but none
// were satisfied.
if (!OneHadNoPredicate)
OS << " return 0;\n";
OS << " return Register();\n";
OS << "}\n";
OS << "\n";
}
@@ -714,7 +714,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
MVT::SimpleValueType RetVT = RI.first;
const PredMap &PM = RI.second;
OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_"
OS << "Register fastEmit_" << getLegalCName(Opcode) << "_"
<< getLegalCName(std::string(getEnumName(VT))) << "_"
<< getLegalCName(std::string(getEnumName(RetVT))) << "_";
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
@@ -727,7 +727,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
}
// Emit one function for the type that demultiplexes on return type.
OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_"
OS << "Register fastEmit_" << getLegalCName(Opcode) << "_"
<< getLegalCName(std::string(getEnumName(VT))) << "_";
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
OS << "(MVT RetVT";
@@ -746,11 +746,11 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
Operands.PrintArguments(OS);
OS << ");\n";
}
OS << " default: return 0;\n}\n}\n\n";
OS << " default: return Register();\n}\n}\n\n";
} else {
// Non-variadic return type.
OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_"
OS << "Register fastEmit_" << getLegalCName(Opcode) << "_"
<< getLegalCName(std::string(getEnumName(VT))) << "_";
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
OS << "(MVT RetVT";
@@ -760,7 +760,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
OS << ") {\n";
OS << " if (RetVT.SimpleTy != " << getEnumName(RM.begin()->first)
<< ")\n return 0;\n";
<< ")\n return Register();\n";
const PredMap &PM = RM.begin()->second;
@@ -769,7 +769,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
}
// Emit one function for the opcode that demultiplexes based on the type.
OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_";
OS << "Register fastEmit_" << getLegalCName(Opcode) << "_";
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
OS << "(MVT VT, MVT RetVT";
if (!Operands.empty())
@@ -789,7 +789,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
Operands.PrintArguments(OS);
OS << ");\n";
}
OS << " default: return 0;\n";
OS << " default: return Register();\n";
OS << " }\n";
OS << "}\n";
OS << "\n";
@@ -800,7 +800,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
// Emit one function for the operand signature that demultiplexes based
// on opcode and type.
OS << "unsigned fastEmit_";
OS << "Register fastEmit_";
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
OS << "(MVT VT, MVT RetVT, unsigned Opcode";
if (!Operands.empty())
@@ -854,7 +854,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
Operands.PrintArguments(OS);
OS << ");\n";
}
OS << " default: return 0;\n";
OS << " default: return Register();\n";
OS << " }\n";
OS << "}\n";
OS << "\n";