mirror of
https://github.com/intel/llvm.git
synced 2026-01-20 19:07:53 +08:00
[DAGCombine] Improve bswap lowering for machines that support bit rotates (#164848)
Source: Hacker's delight.
This commit is contained in:
AZero13
GitHub
@@ -9899,6 +9899,18 @@ SDValue TargetLowering::expandBSWAP(SDNode *N, SelectionDAG &DAG) const {
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// Use a rotate by 8. This can be further expanded if necessary.
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return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
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case MVT::i32:
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// This is meant for ARM speficially, which has ROTR but no ROTL.
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if (isOperationLegalOrCustom(ISD::ROTR, VT)) {
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SDValue Mask = DAG.getConstant(0x00FF00FF, dl, VT);
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// (x & 0x00FF00FF) rotr 8 | (x rotl 8) & 0x00FF00FF
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SDValue And = DAG.getNode(ISD::AND, dl, VT, Op, Mask);
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SDValue Rotr =
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DAG.getNode(ISD::ROTR, dl, VT, And, DAG.getConstant(8, dl, SHVT));
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SDValue Rotl =
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DAG.getNode(ISD::ROTR, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
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SDValue And2 = DAG.getNode(ISD::AND, dl, VT, Rotl, Mask);
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return DAG.getNode(ISD::OR, dl, VT, Rotr, And2);
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}
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Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
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Tmp3 = DAG.getNode(ISD::AND, dl, VT, Op,
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DAG.getConstant(0xFF00, dl, VT));
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@@ -53,14 +53,12 @@ define i32 @load_i32_by_i8_bswap(ptr %arg) {
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; BSWAP is not supported by 32 bit target
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; CHECK-LABEL: load_i32_by_i8_bswap:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #255
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: mov r1, #65280
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r1, r1, r0, lsr #8
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; CHECK-NEXT: orr r1, r1, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: orr r1, r1, #16711680
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; CHECK-NEXT: and r2, r0, r1
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; CHECK-NEXT: and r0, r1, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r2, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
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@@ -223,21 +221,16 @@ define i32 @load_i32_by_i16_i8(ptr %arg) {
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define i64 @load_i64_by_i8_bswap(ptr %arg) {
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; CHECK-LABEL: load_i64_by_i8_bswap:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #255
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; CHECK-NEXT: ldr r1, [r0]
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; CHECK-NEXT: mov r12, #65280
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; CHECK-NEXT: ldr r0, [r0, #4]
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r3, r12, r0, lsr #8
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; CHECK-NEXT: orr r3, r3, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: and r2, r12, r1, lsr #8
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; CHECK-NEXT: orr r0, r0, r3
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; CHECK-NEXT: and r3, r1, #65280
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; CHECK-NEXT: orr r2, r2, r1, lsr #24
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; CHECK-NEXT: lsl r1, r1, #24
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; CHECK-NEXT: orr r1, r1, r3, lsl #8
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; CHECK-NEXT: orr r1, r1, r2
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; CHECK-NEXT: orr r2, r2, #16711680
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; CHECK-NEXT: and r3, r0, r2
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; CHECK-NEXT: and r0, r2, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r3, ror #8
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; CHECK-NEXT: and r3, r1, r2
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; CHECK-NEXT: and r1, r2, r1, ror #24
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; CHECK-NEXT: orr r1, r1, r3, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
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@@ -377,14 +370,12 @@ define i64 @load_i64_by_i8(ptr %arg) {
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define i32 @load_i32_by_i8_nonzero_offset(ptr %arg) {
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; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #255
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; CHECK-NEXT: ldr r0, [r0, #1]
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; CHECK-NEXT: mov r1, #65280
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r1, r1, r0, lsr #8
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; CHECK-NEXT: orr r1, r1, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: orr r1, r1, #16711680
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; CHECK-NEXT: and r2, r0, r1
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; CHECK-NEXT: and r0, r1, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r2, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset:
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@@ -434,14 +425,12 @@ define i32 @load_i32_by_i8_nonzero_offset(ptr %arg) {
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define i32 @load_i32_by_i8_neg_offset(ptr %arg) {
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; CHECK-LABEL: load_i32_by_i8_neg_offset:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #255
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; CHECK-NEXT: ldr r0, [r0, #-4]
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; CHECK-NEXT: mov r1, #65280
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r1, r1, r0, lsr #8
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; CHECK-NEXT: orr r1, r1, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: orr r1, r1, #16711680
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; CHECK-NEXT: and r2, r0, r1
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; CHECK-NEXT: and r0, r1, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r2, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset:
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@@ -587,14 +576,12 @@ declare i16 @llvm.bswap.i16(i16)
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define i32 @load_i32_by_bswap_i16(ptr %arg) {
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; CHECK-LABEL: load_i32_by_bswap_i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #255
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: mov r1, #65280
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r1, r1, r0, lsr #8
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; CHECK-NEXT: orr r1, r1, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: orr r1, r1, #16711680
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; CHECK-NEXT: and r2, r0, r1
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; CHECK-NEXT: and r0, r1, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r2, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
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@@ -667,14 +654,12 @@ define i32 @load_i32_by_i8_base_offset_index(ptr %arg, i32 %i) {
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; CHECK-LABEL: load_i32_by_i8_base_offset_index:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: add r0, r0, r1
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; CHECK-NEXT: mov r1, #65280
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; CHECK-NEXT: mov r1, #255
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; CHECK-NEXT: orr r1, r1, #16711680
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; CHECK-NEXT: ldr r0, [r0, #12]
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r1, r1, r0, lsr #8
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; CHECK-NEXT: orr r1, r1, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: and r2, r0, r1
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; CHECK-NEXT: and r0, r1, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r2, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index:
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@@ -733,14 +718,12 @@ define i32 @load_i32_by_i8_base_offset_index_2(ptr %arg, i32 %i) {
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; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: add r0, r1, r0
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; CHECK-NEXT: mov r1, #65280
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; CHECK-NEXT: mov r1, #255
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; CHECK-NEXT: orr r1, r1, #16711680
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; CHECK-NEXT: ldr r0, [r0, #13]
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r1, r1, r0, lsr #8
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; CHECK-NEXT: orr r1, r1, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: and r2, r0, r1
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; CHECK-NEXT: and r0, r1, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r2, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2:
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@@ -117,14 +117,12 @@ define i32 @load_i32_by_i8_bswap(ptr %arg) {
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; BSWAP is not supported by 32 bit target
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; CHECK-LABEL: load_i32_by_i8_bswap:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #255
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: mov r1, #65280
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r1, r1, r0, lsr #8
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; CHECK-NEXT: orr r1, r1, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: orr r1, r1, #16711680
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; CHECK-NEXT: and r2, r0, r1
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; CHECK-NEXT: and r0, r1, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r2, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
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@@ -237,21 +235,16 @@ define i64 @load_i64_by_i8(ptr %arg) {
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define i64 @load_i64_by_i8_bswap(ptr %arg) {
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; CHECK-LABEL: load_i64_by_i8_bswap:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #255
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; CHECK-NEXT: ldr r1, [r0]
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; CHECK-NEXT: mov r12, #65280
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; CHECK-NEXT: ldr r0, [r0, #4]
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r3, r12, r0, lsr #8
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; CHECK-NEXT: orr r3, r3, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: and r2, r12, r1, lsr #8
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; CHECK-NEXT: orr r0, r0, r3
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; CHECK-NEXT: and r3, r1, #65280
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; CHECK-NEXT: orr r2, r2, r1, lsr #24
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; CHECK-NEXT: lsl r1, r1, #24
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; CHECK-NEXT: orr r1, r1, r3, lsl #8
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; CHECK-NEXT: orr r1, r1, r2
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; CHECK-NEXT: orr r2, r2, #16711680
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; CHECK-NEXT: and r3, r0, r2
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; CHECK-NEXT: and r0, r2, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r3, ror #8
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; CHECK-NEXT: and r3, r1, r2
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; CHECK-NEXT: and r1, r2, r1, ror #24
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; CHECK-NEXT: orr r1, r1, r3, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
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@@ -413,14 +406,12 @@ define i32 @load_i32_by_i8_neg_offset(ptr %arg) {
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define i32 @load_i32_by_i8_nonzero_offset_bswap(ptr %arg) {
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; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #255
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; CHECK-NEXT: ldr r0, [r0, #1]
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; CHECK-NEXT: mov r1, #65280
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r1, r1, r0, lsr #8
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; CHECK-NEXT: orr r1, r1, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: orr r1, r1, #16711680
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; CHECK-NEXT: and r2, r0, r1
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; CHECK-NEXT: and r0, r1, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r2, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap:
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@@ -469,14 +460,12 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(ptr %arg) {
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define i32 @load_i32_by_i8_neg_offset_bswap(ptr %arg) {
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; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #255
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; CHECK-NEXT: ldr r0, [r0, #-4]
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; CHECK-NEXT: mov r1, #65280
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r1, r1, r0, lsr #8
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; CHECK-NEXT: orr r1, r1, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: orr r1, r1, #16711680
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; CHECK-NEXT: and r2, r0, r1
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; CHECK-NEXT: and r0, r1, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r2, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap:
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@@ -527,14 +516,12 @@ declare i16 @llvm.bswap.i16(i16)
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define i32 @load_i32_by_bswap_i16(ptr %arg) {
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; CHECK-LABEL: load_i32_by_bswap_i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #255
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: mov r1, #65280
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; CHECK-NEXT: and r2, r0, #65280
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; CHECK-NEXT: and r1, r1, r0, lsr #8
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; CHECK-NEXT: orr r1, r1, r0, lsr #24
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; CHECK-NEXT: lsl r0, r0, #24
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; CHECK-NEXT: orr r0, r0, r2, lsl #8
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: orr r1, r1, #16711680
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; CHECK-NEXT: and r2, r0, r1
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; CHECK-NEXT: and r0, r1, r0, ror #24
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; CHECK-NEXT: orr r0, r0, r2, ror #8
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; CHECK-NEXT: mov pc, lr
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;
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; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
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