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Revert "[mlir][vector] Add Vector-dialect interleave-to-shuffle pattern, enable in VectorToSPIRV" (#92006)

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Reverts llvm/llvm-project#91800

Reason: https://lab.llvm.org/buildbot/#/builders/268/builds/13935
This commit is contained in:
Benoit Jacob
2024-05-13 13:50:27 -04:00
committed by GitHub
parent 0df67fa212
commit 5df01ed79c
6 changed files with 0 additions and 88 deletions
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14
mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
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@@ -306,20 +306,6 @@ def ApplyLowerInterleavePatternsOp : Op<Transform_Dialect,
let assemblyFormat = "attr-dict";
}
def ApplyInterleaveToShufflePatternsOp : Op<Transform_Dialect,
"apply_patterns.vector.interleave_to_shuffle",
[DeclareOpInterfaceMethods<PatternDescriptorOpInterface>]> {
let description = [{
Indicates that 1D vector interleave operations should be rewritten as
vector shuffle operations.
This is motivated by some current codegen backends not handling vector
interleave operations.
}];
let assemblyFormat = "attr-dict";
}
def ApplyRewriteNarrowTypePatternsOp : Op<Transform_Dialect,
"apply_patterns.vector.rewrite_narrow_types",
[DeclareOpInterfaceMethods<PatternDescriptorOpInterface>]> {

3
mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
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@@ -273,9 +273,6 @@ void populateVectorInterleaveLoweringPatterns(RewritePatternSet &patterns,
int64_t targetRank = 1,
PatternBenefit benefit = 1);
void populateVectorInterleaveToShufflePatterns(RewritePatternSet &patterns,
PatternBenefit benefit = 1);
} // namespace vector
} // namespace mlir
#endif // MLIR_DIALECT_VECTOR_TRANSFORMS_LOWERINGPATTERNS_H

4
mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
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@@ -18,7 +18,6 @@
#include "mlir/Dialect/SPIRV/IR/SPIRVTypes.h"
#include "mlir/Dialect/SPIRV/Transforms/SPIRVConversion.h"
#include "mlir/Dialect/Vector/IR/VectorOps.h"
#include "mlir/Dialect/Vector/Transforms/LoweringPatterns.h"
#include "mlir/IR/Attributes.h"
#include "mlir/IR/BuiltinAttributes.h"
#include "mlir/IR/BuiltinTypes.h"
@@ -829,9 +828,6 @@ void mlir::populateVectorToSPIRVPatterns(SPIRVTypeConverter &typeConverter,
// than the generic one that extracts all elements.
patterns.add<VectorReductionToFPDotProd>(typeConverter, patterns.getContext(),
PatternBenefit(2));
// Need this until vector.interleave is handled.
vector::populateVectorInterleaveToShufflePatterns(patterns);
}
void mlir::populateVectorReductionToSPIRVDotProductPatterns(

5
mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
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@@ -164,11 +164,6 @@ void transform::ApplyLowerInterleavePatternsOp::populatePatterns(
vector::populateVectorInterleaveLoweringPatterns(patterns);
}
void transform::ApplyInterleaveToShufflePatternsOp::populatePatterns(
RewritePatternSet &patterns) {
vector::populateVectorInterleaveToShufflePatterns(patterns);
}
void transform::ApplyRewriteNarrowTypePatternsOp::populatePatterns(
RewritePatternSet &patterns) {
populateVectorNarrowTypeRewritePatterns(patterns);

41
mlir/lib/Dialect/Vector/Transforms/LowerVectorInterleave.cpp
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@@ -16,7 +16,6 @@
#include "mlir/Dialect/Vector/Utils/VectorUtils.h"
#include "mlir/IR/BuiltinTypes.h"
#include "mlir/IR/PatternMatch.h"
#include "mlir/Support/LogicalResult.h"
#define DEBUG_TYPE "vector-interleave-lowering"
@@ -78,49 +77,9 @@ private:
int64_t targetRank = 1;
};
/// Rewrite vector.interleave op into an equivalent vector.shuffle op, when
/// applicable: `sourceType` must be 1D and non-scalable.
///
/// Example:
///
/// ```mlir
/// vector.interleave %a, %b : vector<7xi16>
/// ```
///
/// Is rewritten into:
///
/// ```mlir
/// vector.shuffle %arg0, %arg1 [0, 7, 1, 8, 2, 9, 3, 10, 4, 11, 5, 12, 6, 13]
/// : vector<7xi16>, vector<7xi16>
/// ```
class InterleaveToShuffle : public OpRewritePattern<vector::InterleaveOp> {
public:
InterleaveToShuffle(MLIRContext *context, PatternBenefit benefit = 1)
: OpRewritePattern(context, benefit) {};
LogicalResult matchAndRewrite(vector::InterleaveOp op,
PatternRewriter &rewriter) const override {
VectorType sourceType = op.getSourceVectorType();
if (sourceType.getRank() != 1 || sourceType.isScalable()) {
return failure();
}
int64_t n = sourceType.getNumElements();
auto seq = llvm::seq<int64_t>(2 * n);
auto zip = llvm::to_vector(llvm::map_range(
seq, [n](int64_t i) { return (i % 2 ? n : 0) + i / 2; }));
rewriter.replaceOpWithNewOp<ShuffleOp>(op, op.getLhs(), op.getRhs(), zip);
return success();
}
};
} // namespace
void mlir::vector::populateVectorInterleaveLoweringPatterns(
RewritePatternSet &patterns, int64_t targetRank, PatternBenefit benefit) {
patterns.add<UnrollInterleaveOp>(targetRank, patterns.getContext(), benefit);
}
void mlir::vector::populateVectorInterleaveToShufflePatterns(
RewritePatternSet &patterns, PatternBenefit benefit) {
patterns.add<InterleaveToShuffle>(patterns.getContext(), benefit);
}

21
mlir/test/Dialect/Vector/vector-interleave-to-shuffle.mlir
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@@ -1,21 +0,0 @@
// RUN: mlir-opt %s --transform-interpreter | FileCheck %s
// CHECK-LABEL: @vector_interleave_to_shuffle
func.func @vector_interleave_to_shuffle(%a: vector<7xi16>, %b: vector<7xi16>) -> vector<14xi16>
{
%0 = vector.interleave %a, %b : vector<7xi16>
return %0 : vector<14xi16>
}
// CHECK: vector.shuffle %arg0, %arg1 [0, 7, 1, 8, 2, 9, 3, 10, 4, 11, 5, 12, 6, 13] : vector<7xi16>, vector<7xi16>
module attributes {transform.with_named_sequence} {
transform.named_sequence @__transform_main(%module_op: !transform.any_op {transform.readonly}) {
%f = transform.structured.match ops{["func.func"]} in %module_op
: (!transform.any_op) -> !transform.any_op
transform.apply_patterns to %f {
transform.apply_patterns.vector.interleave_to_shuffle
} : !transform.any_op
transform.yield
}
}