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Transform illegal intrinsics to V_ILLEGAL
Related tasks: - SWDEV-240194 - SWDEV-309417 - SWDEV-334876 Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D123693
This commit is contained in:
Leon Clark
committed by
Thomas Preud'homme
Thomas Preud'homme
parent
b1356504e6
commit
6a275cd53c
@@ -6632,8 +6632,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
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Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx90a,
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NumVDataDwords, NumVAddrDwords);
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if (Opcode == -1)
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report_fatal_error(
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"requested image instruction is not supported on this GPU");
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return makeV_ILLEGAL(Op, DAG);
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}
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if (Opcode == -1 &&
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Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
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@@ -7823,6 +7822,9 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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unsigned Opcode = 0;
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switch (IntrID) {
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case Intrinsic::amdgcn_global_atomic_fadd:
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if (!Subtarget->hasAtomicFaddNoRtnInsts())
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return makeV_ILLEGAL(Op, DAG);
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LLVM_FALLTHROUGH;
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case Intrinsic::amdgcn_flat_atomic_fadd: {
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EVT VT = Op.getOperand(3).getValueType();
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return DAG.getAtomic(ISD::ATOMIC_LOAD_FADD, DL, VT,
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@@ -8390,6 +8392,27 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
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}
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}
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SDValue SITargetLowering::makeV_ILLEGAL(SDValue Op, SelectionDAG & DAG) const {
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// Create the V_ILLEGAL node.
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SDLoc DL(Op);
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auto Opcode = Subtarget->getGeneration() < AMDGPUSubtarget::GFX10 ?
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AMDGPU::V_ILLEGAL_gfx6_gfx7_gfx8_gfx9 : AMDGPU::V_ILLEGAL;
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auto EntryNode = DAG.getEntryNode();
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auto IllegalNode = DAG.getMachineNode(Opcode, DL, MVT::Other, EntryNode);
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auto IllegalVal = SDValue(IllegalNode, 0u);
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// Add the V_ILLEGAL node to the root chain to prevent its removal.
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auto Chains = SmallVector<SDValue, 2u>();
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Chains.push_back(IllegalVal);
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Chains.push_back(DAG.getRoot());
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auto Root = DAG.getTokenFactor(SDLoc(Chains.back()), Chains);
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DAG.setRoot(Root);
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// Merge with UNDEF to satisfy return value requirements.
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auto UndefVal = DAG.getUNDEF(Op.getValueType());
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return DAG.getMergeValues({UndefVal, IllegalVal}, DL);
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}
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// The raw.(t)buffer and struct.(t)buffer intrinsics have two offset args:
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// offset (the offset that is included in bounds checking and swizzling, to be
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// split between the instruction's voffset and immoffset fields) and soffset
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@@ -87,6 +87,8 @@ private:
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SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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SDValue makeV_ILLEGAL(SDValue Op, SelectionDAG &DAG) const;
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// The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
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// (the offset that is included in bounds checking and swizzling, to be split
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// between the instruction's voffset and immoffset fields) and soffset (the
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@@ -3356,3 +3356,25 @@ def G_FPTRUNC_ROUND_DOWNWARD : AMDGPUGenericInstruction {
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let InOperandList = (ins type1:$src0);
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let hasSideEffects = 0;
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}
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//============================================================================//
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// Dummy Instructions
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//============================================================================//
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def V_ILLEGAL_gfx6_gfx7_gfx8_gfx9 : Enc32, InstSI<(outs), (ins), "v_illegal"> {
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let Inst{31-0} = 0xFFFFFFFF;
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let FixedSize = 1;
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let Size = 4;
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let Uses = [EXEC];
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let hasSideEffects = 1;
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let SubtargetPredicate = isGFX6GFX7GFX8GFX9;
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}
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def V_ILLEGAL : Enc32, InstSI<(outs), (ins), "v_illegal"> {
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let Inst{31-0} = 0x00000000;
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let FixedSize = 1;
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let Size = 4;
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let Uses = [EXEC];
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let hasSideEffects = 1;
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let SubtargetPredicate = isGFX10Plus;
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}
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63
llvm/test/CodeGen/AMDGPU/v_illegal-atomics.ll
Normal file
63
llvm/test/CodeGen/AMDGPU/v_illegal-atomics.ll
Normal file
@@ -0,0 +1,63 @@
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; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX906-ASM %s
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; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX908-ASM %s
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; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX90A-ASM %s
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; RUN: llc -march=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX940-ASM %s
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; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1030-ASM %s
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1100-ASM %s
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; GFX906-ASM-LABEL: fadd_test:
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; GFX906-ASM-NOT: global_atomic_add_f32
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; GFX906-ASM: v_illegal
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; GFX908-ASM-LABEL: fadd_test:
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; GFX908-ASM-NOT: v_illegal
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; GFX908-ASM: global_atomic_add_f32
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; GFX90A-ASM-LABEL: fadd_test:
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; GFX90A-ASM-NOT: v_illegal
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; GFX90A-ASM: global_atomic_add_f32
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; GFX940-ASM-LABEL: fadd_test:
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; GFX940-ASM-NOT: v_illegal
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; GFX940-ASM: global_atomic_add_f32
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; GFX1030-ASM-LABEL: fadd_test:
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; GFX1030-ASM-NOT: global_atomic_add_f32
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; GFX1030-ASM: v_illegal
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; GFX1100-ASM-LABEL: fadd_test:
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; GFX1100-ASM-NOT: v_illegal
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; GFX1100-ASM: global_atomic_add_f32
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx906 -d - | FileCheck --check-prefix=GFX906-OBJ %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx908 -d - | FileCheck --check-prefix=GFX908-OBJ %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx90a -d - | FileCheck --check-prefix=GFX90A-OBJ %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx940 -d - | FileCheck --check-prefix=GFX940-OBJ %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx1030 -d - | FileCheck --check-prefix=GFX1030-OBJ %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx1100 -d - | FileCheck --check-prefix=GFX1100-OBJ %s
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; GFX906-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX906-OBJ-NEXT: v_illegal // 000000000004: FFFFFFFF
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; GFX908-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX908-OBJ-NEXT: global_atomic_add_f32
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; GFX90A-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX90A-OBJ-NEXT: global_atomic_add_f32
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; GFX940-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-OBJ-NEXT: global_atomic_add_f32
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; GFX1030-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1030-OBJ-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX1030-OBJ-NEXT: v_illegal // 000000000008: 00000000
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; GFX1100-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1100-OBJ-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX1100-OBJ-NEXT: global_atomic_add_f32 v[0:1], v2, off
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define fastcc void @fadd_test(float addrspace(1)* nocapture noundef %0, float noundef %1) unnamed_addr {
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%3 = tail call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* noundef %0, float noundef %1)
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ret void
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}
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declare float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* nocapture, float)
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40
llvm/test/CodeGen/AMDGPU/v_illegal-image_sample.ll
Normal file
40
llvm/test/CodeGen/AMDGPU/v_illegal-image_sample.ll
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@@ -0,0 +1,40 @@
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; RUN: llc -O0 -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX906 %s
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; RUN: llc -O0 -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX908 %s
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; RUN: llc -O0 -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX90A %s
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; RUN: llc -O0 -march=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX940 %s
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; RUN: llc -O0 -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1030 %s
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; RUN: llc -O0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1100 %s
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; GFX906-LABEL: image_sample_test:
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; GFX906-NOT: v_illegal
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; GFX906: image_sample_lz
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; GFX908-LABEL: image_sample_test:
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; GFX908-NOT: v_illegal
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; GFX908: image_sample_lz
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; GFX90A-LABEL: image_sample_test:
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; GFX90A-NOT: image_sample_lz
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; GFX90A: v_illegal
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; GFX940-LABEL: image_sample_test:
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; GFX940-NOT: image_sample_lz
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; GFX940: v_illegal
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; GFX1030-LABEL: image_sample_test:
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; GFX1030-NOT: v_illegal
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; GFX1030: image_sample_lz
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; GFX1100-LABEL: image_sample_test:
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; GFX1100-NOT: v_illegal
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; GFX1100: image_sample_lz
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define amdgpu_kernel void @image_sample_test(<4 x float> addrspace(1)* %out, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) {
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%result = tail call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 false, i32 0, i32 0)
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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declare <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg)
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14
llvm/test/MC/AMDGPU/v_illegal-atomics.s
Normal file
14
llvm/test/MC/AMDGPU/v_illegal-atomics.s
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@@ -0,0 +1,14 @@
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx906 -show-encoding %s | FileCheck --check-prefix=GFX906 %s
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck --check-prefix=GFX908 %s
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck --check-prefix=GFX90A %s
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck --check-prefix=GFX940 %s
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX1030 %s
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX1100 %s
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v_illegal
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// GFX906: encoding: [0xff,0xff,0xff,0xff]
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// GFX908: encoding: [0xff,0xff,0xff,0xff]
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// GFX90A: encoding: [0xff,0xff,0xff,0xff]
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// GFX940: encoding: [0xff,0xff,0xff,0xff]
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// GFX1030: encoding: [0x00,0x00,0x00,0x00]
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// GFX1100: encoding: [0x00,0x00,0x00,0x00]
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