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Add SysV Abi for PPC64le

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Summary:
This patch implements the ABI Plugin for PPC64le. It was based on the
ABI for PPC64. It also enables LLDB to evaluate expressions using JIT.

Reviewers: labath, clayborg, jhibbits, davide

Reviewed By: labath, clayborg, jhibbits, davide

Subscribers: davide, JDevlieghere, chmeee, emaste, jhibbits, hfinkel, lldb-commits, nemanjai, luporl, lbianc, mgorny, anajuliapc, kbarton

Differential Revision: https://reviews.llvm.org/D41702
Patch by Alexandre Yukio Yamashita <alexandre.yamashita@eldorado.org.br>

llvm-svn: 323100
This commit is contained in:
Pavel Labath
2018-01-22 11:27:43 +00:00
parent 0018ca8462
commit 6a92e99b64
5 changed files with 716 additions and 441 deletions
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558
lldb/source/Plugins/ABI/SysV-ppc64/ABISysV_ppc64.cpp
View File

@@ -33,191 +33,38 @@
#include "lldb/Utility/DataExtractor.h"
#include "lldb/Utility/Log.h"
#include "lldb/Utility/Status.h"
#include "Utility/PPC64_DWARF_Registers.h"
#include "Utility/PPC64LE_DWARF_Registers.h"
#define DECLARE_REGISTER_INFOS_PPC64_STRUCT
#include "Plugins/Process/Utility/RegisterInfos_ppc64.h"
#undef DECLARE_REGISTER_INFOS_PPC64_STRUCT
#define DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
#include "Plugins/Process/Utility/RegisterInfos_ppc64le.h"
#undef DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
using namespace lldb;
using namespace lldb_private;
enum dwarf_regnums {
dwarf_r0 = 0,
dwarf_r1,
dwarf_r2,
dwarf_r3,
dwarf_r4,
dwarf_r5,
dwarf_r6,
dwarf_r7,
dwarf_r8,
dwarf_r9,
dwarf_r10,
dwarf_r11,
dwarf_r12,
dwarf_r13,
dwarf_r14,
dwarf_r15,
dwarf_r16,
dwarf_r17,
dwarf_r18,
dwarf_r19,
dwarf_r20,
dwarf_r21,
dwarf_r22,
dwarf_r23,
dwarf_r24,
dwarf_r25,
dwarf_r26,
dwarf_r27,
dwarf_r28,
dwarf_r29,
dwarf_r30,
dwarf_r31,
dwarf_f0,
dwarf_f1,
dwarf_f2,
dwarf_f3,
dwarf_f4,
dwarf_f5,
dwarf_f6,
dwarf_f7,
dwarf_f8,
dwarf_f9,
dwarf_f10,
dwarf_f11,
dwarf_f12,
dwarf_f13,
dwarf_f14,
dwarf_f15,
dwarf_f16,
dwarf_f17,
dwarf_f18,
dwarf_f19,
dwarf_f20,
dwarf_f21,
dwarf_f22,
dwarf_f23,
dwarf_f24,
dwarf_f25,
dwarf_f26,
dwarf_f27,
dwarf_f28,
dwarf_f29,
dwarf_f30,
dwarf_f31,
dwarf_cr,
dwarf_fpscr,
dwarf_xer = 101,
dwarf_lr = 108,
dwarf_ctr,
dwarf_pc,
dwarf_cfa,
};
// Note that the size and offset will be updated by platform-specific classes.
#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \
{ \
#reg, alt, 8, 0, eEncodingUint, eFormatHex, {kind1, kind2, kind3, kind4 }, \
nullptr, nullptr, nullptr, 0 \
}
static const RegisterInfo g_register_infos[] = {
// General purpose registers. eh_frame, DWARF,
// Generic, Process Plugin
DEFINE_GPR(r0, nullptr, dwarf_r0, dwarf_r0, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r1, "sp", dwarf_r1, dwarf_r1, LLDB_REGNUM_GENERIC_SP,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r2, nullptr, dwarf_r2, dwarf_r2, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r3, "arg1", dwarf_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG1,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r4, "arg2", dwarf_r4, dwarf_r4, LLDB_REGNUM_GENERIC_ARG2,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r5, "arg3", dwarf_r5, dwarf_r5, LLDB_REGNUM_GENERIC_ARG3,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r6, "arg4", dwarf_r6, dwarf_r6, LLDB_REGNUM_GENERIC_ARG4,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r7, "arg5", dwarf_r7, dwarf_r7, LLDB_REGNUM_GENERIC_ARG5,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r8, "arg6", dwarf_r8, dwarf_r8, LLDB_REGNUM_GENERIC_ARG6,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r9, "arg7", dwarf_r9, dwarf_r9, LLDB_REGNUM_GENERIC_ARG7,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r10, "arg8", dwarf_r10, dwarf_r10, LLDB_REGNUM_GENERIC_ARG8,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r11, nullptr, dwarf_r11, dwarf_r11, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r12, nullptr, dwarf_r12, dwarf_r12, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r13, nullptr, dwarf_r13, dwarf_r13, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r14, nullptr, dwarf_r14, dwarf_r14, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r15, nullptr, dwarf_r15, dwarf_r15, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r16, nullptr, dwarf_r16, dwarf_r16, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r17, nullptr, dwarf_r17, dwarf_r17, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r18, nullptr, dwarf_r18, dwarf_r18, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r19, nullptr, dwarf_r19, dwarf_r19, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r20, nullptr, dwarf_r20, dwarf_r20, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r21, nullptr, dwarf_r21, dwarf_r21, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r22, nullptr, dwarf_r22, dwarf_r22, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r23, nullptr, dwarf_r23, dwarf_r23, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r24, nullptr, dwarf_r24, dwarf_r24, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r25, nullptr, dwarf_r25, dwarf_r25, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r26, nullptr, dwarf_r26, dwarf_r26, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r27, nullptr, dwarf_r27, dwarf_r27, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r28, nullptr, dwarf_r28, dwarf_r28, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r29, nullptr, dwarf_r29, dwarf_r29, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r30, nullptr, dwarf_r30, dwarf_r30, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(r31, nullptr, dwarf_r31, dwarf_r31, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(lr, "lr", dwarf_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA,
LLDB_INVALID_REGNUM),
DEFINE_GPR(cr, "cr", dwarf_cr, dwarf_cr, LLDB_REGNUM_GENERIC_FLAGS,
LLDB_INVALID_REGNUM),
DEFINE_GPR(xer, "xer", dwarf_xer, dwarf_xer, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(ctr, "ctr", dwarf_ctr, dwarf_ctr, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM),
DEFINE_GPR(pc, "pc", dwarf_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC,
LLDB_INVALID_REGNUM),
{nullptr,
nullptr,
8,
0,
eEncodingUint,
eFormatHex,
{dwarf_cfa, dwarf_cfa, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
nullptr,
nullptr,
nullptr,
0}};
static const uint32_t k_num_register_infos =
llvm::array_lengthof(g_register_infos);
const lldb_private::RegisterInfo *
ABISysV_ppc64::GetRegisterInfoArray(uint32_t &count) {
count = k_num_register_infos;
return g_register_infos;
if (GetByteOrder() == lldb::eByteOrderLittle)
{
count = llvm::array_lengthof (g_register_infos_ppc64le);
return g_register_infos_ppc64le;
} else {
count = llvm::array_lengthof (g_register_infos_ppc64);
return g_register_infos_ppc64;
}
}
size_t ABISysV_ppc64::GetRedZoneSize() const { return 224; }
lldb::ByteOrder ABISysV_ppc64::GetByteOrder() const {
return GetProcessSP()->GetByteOrder();
}
//------------------------------------------------------------------
// Static Functions
//------------------------------------------------------------------
@@ -225,7 +72,8 @@ size_t ABISysV_ppc64::GetRedZoneSize() const { return 224; }
ABISP
ABISysV_ppc64::CreateInstance(lldb::ProcessSP process_sp, const ArchSpec &arch) {
static ABISP g_abi_sp;
if (arch.GetTriple().getArch() == llvm::Triple::ppc64) {
if (arch.GetTriple().getArch() == llvm::Triple::ppc64 ||
arch.GetTriple().getArch() == llvm::Triple::ppc64le) {
if (!g_abi_sp)
g_abi_sp.reset(new ABISysV_ppc64(process_sp));
return g_abi_sp;
@@ -280,28 +128,66 @@ bool ABISysV_ppc64::PrepareTrivialCall(Thread &thread, addr_t sp,
sp &= ~(0xfull); // 16-byte alignment
sp -= 8;
sp -= 544; // allocate frame to save TOC, RA and SP.
Status error;
uint64_t reg_value;
const RegisterInfo *pc_reg_info =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
const RegisterInfo *sp_reg_info =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
ProcessSP process_sp(thread.GetProcess());
const RegisterInfo *lr_reg_info =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
const RegisterInfo *r2_reg_info = reg_ctx->GetRegisterInfoAtIndex(2);
const RegisterInfo *r12_reg_info = reg_ctx->GetRegisterInfoAtIndex(12);
RegisterValue reg_value;
// Save return address onto the stack.
if (log)
log->Printf("Pushing the return address onto the stack: 0x%" PRIx64
": 0x%" PRIx64,
(uint64_t)sp, (uint64_t)return_addr);
"(+16): 0x%" PRIx64, (uint64_t)sp, (uint64_t)return_addr);
if (!process_sp->WritePointerToMemory(sp + 16, return_addr, error))
return false;
// Save return address onto the stack
if (!process_sp->WritePointerToMemory(sp, return_addr, error))
// Write the return address to link register.
if (log)
log->Printf("Writing LR: 0x%" PRIx64, (uint64_t)return_addr);
if (!reg_ctx->WriteRegisterFromUnsigned(lr_reg_info, return_addr))
return false;
// Write target address to %r12 register.
if (log)
log->Printf("Writing R12: 0x%" PRIx64, (uint64_t)func_addr);
if (!reg_ctx->WriteRegisterFromUnsigned(r12_reg_info, func_addr))
return false;
// Read TOC pointer value.
reg_value = reg_ctx->ReadRegisterAsUnsigned(r2_reg_info, 0);
// Write TOC pointer onto the stack.
uint64_t stack_offset;
if (GetByteOrder() == lldb::eByteOrderLittle)
stack_offset = 24;
else
stack_offset = 40;
if (log)
log->Printf("Writing R2 (TOC) at SP(0x%" PRIx64 ")+%d: 0x%" PRIx64,
(uint64_t)(sp + stack_offset), (int) stack_offset, (uint64_t)reg_value);
if (!process_sp->WritePointerToMemory(sp + stack_offset, reg_value, error))
return false;
// Read the current SP value.
reg_value = reg_ctx->ReadRegisterAsUnsigned(sp_reg_info, 0);
// Save current SP onto the stack.
if (log)
log->Printf("Writing SP at SP(0x%" PRIx64 ")+0: 0x%" PRIx64,
(uint64_t)sp, (uint64_t)reg_value);
if (!process_sp->WritePointerToMemory(sp, reg_value, error))
return false;
// %r1 is set to the actual stack value.
if (log)
log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
@@ -365,34 +251,20 @@ bool ABISysV_ppc64::GetArgumentValues(Thread &thread, ValueList &values) const {
if (!sp)
return false;
addr_t current_stack_argument = sp + 48; // jump over return address
uint64_t stack_offset;
if (GetByteOrder() == lldb::eByteOrderLittle)
stack_offset = 32;
else
stack_offset = 48;
// jump over return address.
addr_t current_stack_argument = sp + stack_offset;
uint32_t argument_register_ids[8];
argument_register_ids[0] =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1)
->kinds[eRegisterKindLLDB];
argument_register_ids[1] =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG2)
->kinds[eRegisterKindLLDB];
argument_register_ids[2] =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG3)
->kinds[eRegisterKindLLDB];
argument_register_ids[3] =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG4)
->kinds[eRegisterKindLLDB];
argument_register_ids[4] =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG5)
->kinds[eRegisterKindLLDB];
argument_register_ids[5] =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG6)
->kinds[eRegisterKindLLDB];
argument_register_ids[6] =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG7)
->kinds[eRegisterKindLLDB];
argument_register_ids[7] =
reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG8)
->kinds[eRegisterKindLLDB];
for (size_t i = 0; i < 8; ++i) {
argument_register_ids[i] = reg_ctx->GetRegisterInfo(eRegisterKindGeneric,
LLDB_REGNUM_GENERIC_ARG1 + i)->kinds[eRegisterKindLLDB];
}
unsigned int current_argument_register = 0;
@@ -612,7 +484,8 @@ ValueObjectSP ABISysV_ppc64::GetReturnValueObjectSimple(
} else if (type_flags & eTypeIsVector) {
const size_t byte_size = return_compiler_type.GetByteSize(nullptr);
if (byte_size > 0) {
const RegisterInfo *altivec_reg = reg_ctx->GetRegisterInfoByName("v2", 0);
const RegisterInfo *altivec_reg =
reg_ctx->GetRegisterInfoByName("vr2", 0);
if (altivec_reg) {
if (byte_size <= altivec_reg->byte_size) {
ProcessSP process_sp(thread.GetProcess());
@@ -643,234 +516,28 @@ ValueObjectSP ABISysV_ppc64::GetReturnValueObjectSimple(
return return_valobj_sp;
}
ValueObjectSP ABISysV_ppc64::GetReturnValueObjectImpl(
Thread &thread, CompilerType &return_compiler_type) const {
ValueObjectSP return_valobj_sp;
if (!return_compiler_type)
return return_valobj_sp;
ExecutionContext exe_ctx(thread.shared_from_this());
return_valobj_sp = GetReturnValueObjectSimple(thread, return_compiler_type);
if (return_valobj_sp)
return return_valobj_sp;
RegisterContextSP reg_ctx_sp = thread.GetRegisterContext();
if (!reg_ctx_sp)
return return_valobj_sp;
const size_t bit_width = return_compiler_type.GetBitSize(&thread);
if (return_compiler_type.IsAggregateType()) {
Target *target = exe_ctx.GetTargetPtr();
bool is_memory = true;
if (bit_width <= 128) {
ByteOrder target_byte_order = target->GetArchitecture().GetByteOrder();
DataBufferSP data_sp(new DataBufferHeap(16, 0));
DataExtractor return_ext(data_sp, target_byte_order,
target->GetArchitecture().GetAddressByteSize());
const RegisterInfo *r3_info = reg_ctx_sp->GetRegisterInfoByName("r3", 0);
const RegisterInfo *rdx_info =
reg_ctx_sp->GetRegisterInfoByName("rdx", 0);
RegisterValue r3_value, rdx_value;
reg_ctx_sp->ReadRegister(r3_info, r3_value);
reg_ctx_sp->ReadRegister(rdx_info, rdx_value);
DataExtractor r3_data, rdx_data;
r3_value.GetData(r3_data);
rdx_value.GetData(rdx_data);
uint32_t fp_bytes =
0; // Tracks how much of the xmm registers we've consumed so far
uint32_t integer_bytes =
0; // Tracks how much of the r3/rds registers we've consumed so far
const uint32_t num_children = return_compiler_type.GetNumFields();
// Since we are in the small struct regime, assume we are not in memory.
is_memory = false;
for (uint32_t idx = 0; idx < num_children; idx++) {
std::string name;
uint64_t field_bit_offset = 0;
bool is_signed;
bool is_complex;
uint32_t count;
CompilerType field_compiler_type = return_compiler_type.GetFieldAtIndex(
idx, name, &field_bit_offset, nullptr, nullptr);
const size_t field_bit_width = field_compiler_type.GetBitSize(&thread);
// If there are any unaligned fields, this is stored in memory.
if (field_bit_offset % field_bit_width != 0) {
is_memory = true;
break;
}
uint32_t field_byte_width = field_bit_width / 8;
uint32_t field_byte_offset = field_bit_offset / 8;
DataExtractor *copy_from_extractor = nullptr;
uint32_t copy_from_offset = 0;
if (field_compiler_type.IsIntegerOrEnumerationType(is_signed) ||
field_compiler_type.IsPointerType()) {
if (integer_bytes < 8) {
if (integer_bytes + field_byte_width <= 8) {
// This is in RAX, copy from register to our result structure:
copy_from_extractor = &r3_data;
copy_from_offset = integer_bytes;
integer_bytes += field_byte_width;
} else {
// The next field wouldn't fit in the remaining space, so we
// pushed it to rdx.
copy_from_extractor = &rdx_data;
copy_from_offset = 0;
integer_bytes = 8 + field_byte_width;
}
} else if (integer_bytes + field_byte_width <= 16) {
copy_from_extractor = &rdx_data;
copy_from_offset = integer_bytes - 8;
integer_bytes += field_byte_width;
} else {
// The last field didn't fit. I can't see how that would happen w/o
// the overall size being
// greater than 16 bytes. For now, return a nullptr return value
// object.
return return_valobj_sp;
}
} else if (field_compiler_type.IsFloatingPointType(count, is_complex)) {
// Structs with long doubles are always passed in memory.
if (field_bit_width == 128) {
is_memory = true;
break;
} else if (field_bit_width == 64) {
copy_from_offset = 0;
fp_bytes += field_byte_width;
} else if (field_bit_width == 32) {
// This one is kind of complicated. If we are in an "eightbyte"
// with another float, we'll
// be stuffed into an xmm register with it. If we are in an
// "eightbyte" with one or more ints,
// then we will be stuffed into the appropriate GPR with them.
bool in_gpr;
if (field_byte_offset % 8 == 0) {
// We are at the beginning of one of the eightbytes, so check the
// next element (if any)
if (idx == num_children - 1)
in_gpr = false;
else {
uint64_t next_field_bit_offset = 0;
CompilerType next_field_compiler_type =
return_compiler_type.GetFieldAtIndex(idx + 1, name,
&next_field_bit_offset,
nullptr, nullptr);
if (next_field_compiler_type.IsIntegerOrEnumerationType(
is_signed))
in_gpr = true;
else {
copy_from_offset = 0;
in_gpr = false;
}
}
} else if (field_byte_offset % 4 == 0) {
// We are inside of an eightbyte, so see if the field before us is
// floating point:
// This could happen if somebody put padding in the structure.
if (idx == 0)
in_gpr = false;
else {
uint64_t prev_field_bit_offset = 0;
CompilerType prev_field_compiler_type =
return_compiler_type.GetFieldAtIndex(idx - 1, name,
&prev_field_bit_offset,
nullptr, nullptr);
if (prev_field_compiler_type.IsIntegerOrEnumerationType(
is_signed))
in_gpr = true;
else {
copy_from_offset = 4;
in_gpr = false;
}
}
} else {
is_memory = true;
continue;
}
// Okay, we've figured out whether we are in GPR or XMM, now figure
// out which one.
if (in_gpr) {
if (integer_bytes < 8) {
// This is in RAX, copy from register to our result structure:
copy_from_extractor = &r3_data;
copy_from_offset = integer_bytes;
integer_bytes += field_byte_width;
} else {
copy_from_extractor = &rdx_data;
copy_from_offset = integer_bytes - 8;
integer_bytes += field_byte_width;
}
} else {
fp_bytes += field_byte_width;
}
}
}
// These two tests are just sanity checks. If I somehow get the
// type calculation wrong above it is better to just return nothing
// than to assert or crash.
if (!copy_from_extractor)
return return_valobj_sp;
if (copy_from_offset + field_byte_width >
copy_from_extractor->GetByteSize())
return return_valobj_sp;
copy_from_extractor->CopyByteOrderedData(
copy_from_offset, field_byte_width,
data_sp->GetBytes() + field_byte_offset, field_byte_width,
target_byte_order);
}
if (!is_memory) {
// The result is in our data buffer. Let's make a variable object out
// of it:
return_valobj_sp = ValueObjectConstResult::Create(
&thread, return_compiler_type, ConstString(""), return_ext);
}
}
// FIXME: This is just taking a guess, r3 may very well no longer hold the
// return storage location.
// If we are going to do this right, when we make a new frame we should
// check to see if it uses a memory
// return, and if we are at the first instruction and if so stash away the
// return location. Then we would
// only return the memory return value if we know it is valid.
if (is_memory) {
unsigned r3_id =
reg_ctx_sp->GetRegisterInfoByName("r3", 0)->kinds[eRegisterKindLLDB];
lldb::addr_t storage_addr =
(uint64_t)thread.GetRegisterContext()->ReadRegisterAsUnsigned(r3_id,
0);
return_valobj_sp = ValueObjectMemory::Create(
&thread, "", Address(storage_addr, nullptr), return_compiler_type);
}
}
return return_valobj_sp;
ValueObjectSP ABISysV_ppc64::GetReturnValueObjectImpl(Thread &thread,
CompilerType &return_compiler_type) const {
return GetReturnValueObjectSimple(thread, return_compiler_type);
}
bool ABISysV_ppc64::CreateFunctionEntryUnwindPlan(UnwindPlan &unwind_plan) {
unwind_plan.Clear();
unwind_plan.SetRegisterKind(eRegisterKindDWARF);
uint32_t lr_reg_num = dwarf_lr;
uint32_t sp_reg_num = dwarf_r1;
uint32_t pc_reg_num = dwarf_pc;
uint32_t lr_reg_num;
uint32_t sp_reg_num;
uint32_t pc_reg_num;
if (GetByteOrder() == lldb::eByteOrderLittle) {
lr_reg_num = ppc64le_dwarf::dwarf_lr_ppc64le;
sp_reg_num = ppc64le_dwarf::dwarf_r1_ppc64le;
pc_reg_num = ppc64le_dwarf::dwarf_pc_ppc64le;
} else {
lr_reg_num = ppc64_dwarf::dwarf_lr_ppc64;
sp_reg_num = ppc64_dwarf::dwarf_r1_ppc64;
pc_reg_num = ppc64_dwarf::dwarf_pc_ppc64;
}
UnwindPlan::RowSP row(new UnwindPlan::Row);
@@ -893,23 +560,33 @@ bool ABISysV_ppc64::CreateDefaultUnwindPlan(UnwindPlan &unwind_plan) {
unwind_plan.Clear();
unwind_plan.SetRegisterKind(eRegisterKindDWARF);
uint32_t sp_reg_num = dwarf_r1;
uint32_t pc_reg_num = dwarf_lr;
uint32_t sp_reg_num;
uint32_t pc_reg_num;
uint32_t cr_reg_num;
if (GetByteOrder() == lldb::eByteOrderLittle) {
sp_reg_num = ppc64le_dwarf::dwarf_r1_ppc64le;
pc_reg_num = ppc64le_dwarf::dwarf_lr_ppc64le;
cr_reg_num = ppc64le_dwarf::dwarf_cr_ppc64le;
} else {
sp_reg_num = ppc64_dwarf::dwarf_r1_ppc64;
pc_reg_num = ppc64_dwarf::dwarf_lr_ppc64;
cr_reg_num = ppc64_dwarf::dwarf_cr_ppc64;
}
UnwindPlan::RowSP row(new UnwindPlan::Row);
const int32_t ptr_size = 8;
row->GetCFAValue().SetIsRegisterDereferenced(sp_reg_num);
row->SetRegisterLocationToAtCFAPlusOffset(pc_reg_num, ptr_size * 2, true);
row->SetRegisterLocationToIsCFAPlusOffset(sp_reg_num, 0, true);
row->SetRegisterLocationToAtCFAPlusOffset(dwarf_cr, ptr_size, true);
row->SetRegisterLocationToAtCFAPlusOffset(cr_reg_num, ptr_size, true);
unwind_plan.AppendRow(row);
unwind_plan.SetSourceName("ppc64 default unwind plan");
unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolNo);
unwind_plan.SetReturnAddressRegister(dwarf_lr);
unwind_plan.SetReturnAddressRegister(pc_reg_num);
return true;
}
@@ -920,9 +597,8 @@ bool ABISysV_ppc64::RegisterIsVolatile(const RegisterInfo *reg_info) {
// See "Register Usage" in the
// "System V Application Binary Interface"
// "64-bit PowerPC ELF Application Binary Interface Supplement"
// current version is 1.9 released 2004 at
// http://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf
// current version is 2 released 2015 at
// https://members.openpowerfoundation.org/document/dl/576
bool ABISysV_ppc64::RegisterIsCalleeSaved(const RegisterInfo *reg_info) {
if (reg_info) {
// Preserved registers are :
@@ -954,7 +630,7 @@ bool ABISysV_ppc64::RegisterIsCalleeSaved(const RegisterInfo *reg_info) {
if (name[0] == 's' && name[1] == 'p' && name[2] == '\0') // sp
return true;
if (name[0] == 'f' && name[1] == 'p' && name[2] == '\0') // fp
return true;
return false;
if (name[0] == 'p' && name[1] == 'c' && name[2] == '\0') // pc
return true;
}

2
lldb/source/Plugins/ABI/SysV-ppc64/ABISysV_ppc64.h
View File

@@ -108,6 +108,8 @@ private:
ABISysV_ppc64(lldb::ProcessSP process_sp) : lldb_private::ABI(process_sp) {
// Call CreateInstance instead.
}
lldb::ByteOrder GetByteOrder() const;
};
#endif // liblldb_ABISysV_ppc64_h_

331
lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64.h Normal file
View File

@@ -0,0 +1,331 @@
//===-- RegisterInfos_ppc64.h -----------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifdef DECLARE_REGISTER_INFOS_PPC64_STRUCT
// C Includes
#include <stddef.h>
// Computes the offset of the given GPR_PPC64 in the user data area.
#define GPR_PPC64_OFFSET(regname) (offsetof(GPR_PPC64, regname))
#define FPR_PPC64_OFFSET(regname) (offsetof(FPR_PPC64, regname) \
+ sizeof(GPR_PPC64))
#define VMX_PPC64_OFFSET(regname) (offsetof(VMX_PPC64, regname) \
+ sizeof(GPR_PPC64) + sizeof(FPR_PPC64))
#define GPR_PPC64_SIZE(regname) (sizeof(((GPR_PPC64 *)NULL)->regname))
#include "Utility/PPC64_DWARF_Registers.h"
#include "lldb-ppc64-register-enums.h"
// Note that the size and offset will be updated by platform-specific classes.
#define DEFINE_GPR_PPC64(reg, alt, lldb_kind) \
{ \
#reg, alt, GPR_PPC64_SIZE(reg), GPR_PPC64_OFFSET(reg), lldb::eEncodingUint,\
lldb::eFormatHex, \
{ppc64_dwarf::dwarf_##reg##_ppc64, \
ppc64_dwarf::dwarf_##reg##_ppc64, \
lldb_kind, \
LLDB_INVALID_REGNUM, \
gpr_##reg##_ppc64 }, \
NULL, NULL, NULL, 0 \
}
#define DEFINE_FPR_PPC64(reg, alt, lldb_kind) \
{ \
#reg, alt, 8, FPR_PPC64_OFFSET(reg), lldb::eEncodingIEEE754, \
lldb::eFormatFloat, \
{ppc64_dwarf::dwarf_##reg##_ppc64, \
ppc64_dwarf::dwarf_##reg##_ppc64, lldb_kind, LLDB_INVALID_REGNUM, \
fpr_##reg##_ppc64 }, \
NULL, NULL, NULL, 0 \
}
#define DEFINE_VMX_PPC64(reg, lldb_kind) \
{ \
#reg, NULL, 16, VMX_PPC64_OFFSET(reg), lldb::eEncodingVector, \
lldb::eFormatVectorOfUInt32, \
{ppc64_dwarf::dwarf_##reg##_ppc64, \
ppc64_dwarf::dwarf_##reg##_ppc64, lldb_kind, LLDB_INVALID_REGNUM, \
vmx_##reg##_ppc64 }, \
NULL, NULL, NULL, 0 \
}
// General purpose registers.
// EH_Frame, Generic, Process Plugin
#define PPC64_REGS \
DEFINE_GPR_PPC64(r0, NULL, LLDB_INVALID_REGNUM) \
, DEFINE_GPR_PPC64(r1, "sp", LLDB_REGNUM_GENERIC_SP), \
DEFINE_GPR_PPC64(r2, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r3, "arg1", LLDB_REGNUM_GENERIC_ARG1), \
DEFINE_GPR_PPC64(r4, "arg2", LLDB_REGNUM_GENERIC_ARG2), \
DEFINE_GPR_PPC64(r5, "arg3", LLDB_REGNUM_GENERIC_ARG3), \
DEFINE_GPR_PPC64(r6, "arg4", LLDB_REGNUM_GENERIC_ARG4), \
DEFINE_GPR_PPC64(r7, "arg5", LLDB_REGNUM_GENERIC_ARG5), \
DEFINE_GPR_PPC64(r8, "arg6", LLDB_REGNUM_GENERIC_ARG6), \
DEFINE_GPR_PPC64(r9, "arg7", LLDB_REGNUM_GENERIC_ARG7), \
DEFINE_GPR_PPC64(r10, "arg8", LLDB_REGNUM_GENERIC_ARG8), \
DEFINE_GPR_PPC64(r11, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r12, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r13, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r14, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r15, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r16, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r17, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r18, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r19, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r20, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r21, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r22, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r23, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r24, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r25, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r26, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r27, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r28, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r29, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r30, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(r31, NULL, LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(cr, "cr", LLDB_REGNUM_GENERIC_FLAGS), \
DEFINE_GPR_PPC64(msr, "msr", LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(xer, "xer", LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(lr, "lr", LLDB_REGNUM_GENERIC_RA), \
DEFINE_GPR_PPC64(ctr, "ctr", LLDB_INVALID_REGNUM), \
DEFINE_GPR_PPC64(pc, "pc", LLDB_REGNUM_GENERIC_PC), \
DEFINE_FPR_PPC64(f0, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f1, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f2, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f3, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f4, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f5, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f6, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f7, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f8, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f9, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f10, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f11, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f12, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f13, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f14, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f15, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f16, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f17, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f18, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f19, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f20, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f21, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f22, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f23, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f24, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f25, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f26, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f27, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f28, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f29, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f30, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR_PPC64(f31, NULL, LLDB_INVALID_REGNUM), \
{"fpscr", \
NULL, \
8, \
FPR_PPC64_OFFSET(fpscr), \
lldb::eEncodingUint, \
lldb::eFormatHex, \
{ppc64_dwarf::dwarf_fpscr_ppc64, \
ppc64_dwarf::dwarf_fpscr_ppc64, LLDB_INVALID_REGNUM, \
LLDB_INVALID_REGNUM, fpr_fpscr_ppc64}, \
NULL, \
NULL, \
NULL, \
0}, \
DEFINE_VMX_PPC64(vr0, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr1, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr2, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr3, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr4, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr5, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr6, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr7, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr8, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr9, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr10, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr11, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr12, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr13, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr14, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr15, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr16, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr17, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr18, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr19, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr20, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr21, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr22, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr23, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr24, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr25, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr26, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr27, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr28, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr29, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr30, LLDB_INVALID_REGNUM), \
DEFINE_VMX_PPC64(vr31, LLDB_INVALID_REGNUM), \
{"vscr", \
NULL, \
4, \
VMX_PPC64_OFFSET(vscr), \
lldb::eEncodingUint, \
lldb::eFormatHex, \
{ppc64_dwarf::dwarf_vscr_ppc64, ppc64_dwarf::dwarf_vscr_ppc64, \
LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, vmx_vscr_ppc64}, \
NULL, \
NULL, \
NULL, \
0}, \
{"vrsave", \
NULL, \
4, \
VMX_PPC64_OFFSET(vrsave), \
lldb::eEncodingUint, \
lldb::eFormatHex, \
{ppc64_dwarf::dwarf_vrsave_ppc64, \
ppc64_dwarf::dwarf_vrsave_ppc64, LLDB_INVALID_REGNUM, \
LLDB_INVALID_REGNUM, vmx_vrsave_ppc64}, \
NULL, \
NULL, \
NULL, \
0}, /* */
typedef struct _GPR_PPC64 {
uint64_t r0;
uint64_t r1;
uint64_t r2;
uint64_t r3;
uint64_t r4;
uint64_t r5;
uint64_t r6;
uint64_t r7;
uint64_t r8;
uint64_t r9;
uint64_t r10;
uint64_t r11;
uint64_t r12;
uint64_t r13;
uint64_t r14;
uint64_t r15;
uint64_t r16;
uint64_t r17;
uint64_t r18;
uint64_t r19;
uint64_t r20;
uint64_t r21;
uint64_t r22;
uint64_t r23;
uint64_t r24;
uint64_t r25;
uint64_t r26;
uint64_t r27;
uint64_t r28;
uint64_t r29;
uint64_t r30;
uint64_t r31;
uint64_t cr;
uint64_t msr;
uint64_t xer;
uint64_t lr;
uint64_t ctr;
uint64_t pc;
uint64_t pad[3];
} GPR_PPC64;
typedef struct _FPR_PPC64 {
uint64_t f0;
uint64_t f1;
uint64_t f2;
uint64_t f3;
uint64_t f4;
uint64_t f5;
uint64_t f6;
uint64_t f7;
uint64_t f8;
uint64_t f9;
uint64_t f10;
uint64_t f11;
uint64_t f12;
uint64_t f13;
uint64_t f14;
uint64_t f15;
uint64_t f16;
uint64_t f17;
uint64_t f18;
uint64_t f19;
uint64_t f20;
uint64_t f21;
uint64_t f22;
uint64_t f23;
uint64_t f24;
uint64_t f25;
uint64_t f26;
uint64_t f27;
uint64_t f28;
uint64_t f29;
uint64_t f30;
uint64_t f31;
uint64_t fpscr;
} FPR_PPC64;
typedef struct _VMX_PPC64 {
uint32_t vr0[4];
uint32_t vr1[4];
uint32_t vr2[4];
uint32_t vr3[4];
uint32_t vr4[4];
uint32_t vr5[4];
uint32_t vr6[4];
uint32_t vr7[4];
uint32_t vr8[4];
uint32_t vr9[4];
uint32_t vr10[4];
uint32_t vr11[4];
uint32_t vr12[4];
uint32_t vr13[4];
uint32_t vr14[4];
uint32_t vr15[4];
uint32_t vr16[4];
uint32_t vr17[4];
uint32_t vr18[4];
uint32_t vr19[4];
uint32_t vr20[4];
uint32_t vr21[4];
uint32_t vr22[4];
uint32_t vr23[4];
uint32_t vr24[4];
uint32_t vr25[4];
uint32_t vr26[4];
uint32_t vr27[4];
uint32_t vr28[4];
uint32_t vr29[4];
uint32_t vr30[4];
uint32_t vr31[4];
uint32_t pad[2];
uint32_t vscr[2];
uint32_t vrsave;
} VMX_PPC64;
static lldb_private::RegisterInfo g_register_infos_ppc64[] = {
PPC64_REGS
};
static_assert((sizeof(g_register_infos_ppc64) /
sizeof(g_register_infos_ppc64[0])) ==
k_num_registers_ppc64,
"g_register_infos_powerpc64 has wrong number of register infos");
#undef DEFINE_FPR_PPC64
#undef DEFINE_GPR_PPC64
#undef DEFINE_VMX_PPC64
#endif // DECLARE_REGISTER_INFOS_PPC64_STRUCT

139
lldb/source/Plugins/Process/Utility/lldb-ppc64-register-enums.h Normal file
View File

@@ -0,0 +1,139 @@
//===-- lldb-ppc64-register-enums.h ---------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef lldb_ppc64_register_enums_h
#define lldb_ppc64_register_enums_h
// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
// ---------------------------------------------------------------------------
// Internal codes for all ppc64 registers.
// ---------------------------------------------------------------------------
enum {
k_first_gpr_ppc64,
gpr_r0_ppc64 = k_first_gpr_ppc64,
gpr_r1_ppc64,
gpr_r2_ppc64,
gpr_r3_ppc64,
gpr_r4_ppc64,
gpr_r5_ppc64,
gpr_r6_ppc64,
gpr_r7_ppc64,
gpr_r8_ppc64,
gpr_r9_ppc64,
gpr_r10_ppc64,
gpr_r11_ppc64,
gpr_r12_ppc64,
gpr_r13_ppc64,
gpr_r14_ppc64,
gpr_r15_ppc64,
gpr_r16_ppc64,
gpr_r17_ppc64,
gpr_r18_ppc64,
gpr_r19_ppc64,
gpr_r20_ppc64,
gpr_r21_ppc64,
gpr_r22_ppc64,
gpr_r23_ppc64,
gpr_r24_ppc64,
gpr_r25_ppc64,
gpr_r26_ppc64,
gpr_r27_ppc64,
gpr_r28_ppc64,
gpr_r29_ppc64,
gpr_r30_ppc64,
gpr_r31_ppc64,
gpr_cr_ppc64,
gpr_msr_ppc64,
gpr_xer_ppc64,
gpr_lr_ppc64,
gpr_ctr_ppc64,
gpr_pc_ppc64,
k_last_gpr_ppc64 = gpr_pc_ppc64,
k_first_fpr_ppc64,
fpr_f0_ppc64 = k_first_fpr_ppc64,
fpr_f1_ppc64,
fpr_f2_ppc64,
fpr_f3_ppc64,
fpr_f4_ppc64,
fpr_f5_ppc64,
fpr_f6_ppc64,
fpr_f7_ppc64,
fpr_f8_ppc64,
fpr_f9_ppc64,
fpr_f10_ppc64,
fpr_f11_ppc64,
fpr_f12_ppc64,
fpr_f13_ppc64,
fpr_f14_ppc64,
fpr_f15_ppc64,
fpr_f16_ppc64,
fpr_f17_ppc64,
fpr_f18_ppc64,
fpr_f19_ppc64,
fpr_f20_ppc64,
fpr_f21_ppc64,
fpr_f22_ppc64,
fpr_f23_ppc64,
fpr_f24_ppc64,
fpr_f25_ppc64,
fpr_f26_ppc64,
fpr_f27_ppc64,
fpr_f28_ppc64,
fpr_f29_ppc64,
fpr_f30_ppc64,
fpr_f31_ppc64,
fpr_fpscr_ppc64,
k_last_fpr_ppc64 = fpr_fpscr_ppc64,
k_first_vmx_ppc64,
vmx_vr0_ppc64 = k_first_vmx_ppc64,
vmx_vr1_ppc64,
vmx_vr2_ppc64,
vmx_vr3_ppc64,
vmx_vr4_ppc64,
vmx_vr5_ppc64,
vmx_vr6_ppc64,
vmx_vr7_ppc64,
vmx_vr8_ppc64,
vmx_vr9_ppc64,
vmx_vr10_ppc64,
vmx_vr11_ppc64,
vmx_vr12_ppc64,
vmx_vr13_ppc64,
vmx_vr14_ppc64,
vmx_vr15_ppc64,
vmx_vr16_ppc64,
vmx_vr17_ppc64,
vmx_vr18_ppc64,
vmx_vr19_ppc64,
vmx_vr20_ppc64,
vmx_vr21_ppc64,
vmx_vr22_ppc64,
vmx_vr23_ppc64,
vmx_vr24_ppc64,
vmx_vr25_ppc64,
vmx_vr26_ppc64,
vmx_vr27_ppc64,
vmx_vr28_ppc64,
vmx_vr29_ppc64,
vmx_vr30_ppc64,
vmx_vr31_ppc64,
vmx_vscr_ppc64,
vmx_vrsave_ppc64,
k_last_vmx_ppc64 = vmx_vrsave_ppc64,
k_num_registers_ppc64,
k_num_gpr_registers_ppc64 = k_last_gpr_ppc64 - k_first_gpr_ppc64 + 1,
k_num_fpr_registers_ppc64 = k_last_fpr_ppc64 - k_first_fpr_ppc64 + 1,
k_num_vmx_registers_ppc64 = k_last_vmx_ppc64 - k_first_vmx_ppc64 + 1,
};
#endif // #ifndef lldb_ppc64_register_enums_h

127
lldb/source/Utility/PPC64_DWARF_Registers.h Normal file
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@@ -0,0 +1,127 @@
//===-- PPC64_DWARF_Registers.h ---------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef utility_PPC64_DWARF_Registers_h_
#define utility_PPC64_DWARF_Registers_h_
#include "lldb/lldb-private.h"
namespace ppc64_dwarf {
enum {
dwarf_r0_ppc64 = 0,
dwarf_r1_ppc64,
dwarf_r2_ppc64,
dwarf_r3_ppc64,
dwarf_r4_ppc64,
dwarf_r5_ppc64,
dwarf_r6_ppc64,
dwarf_r7_ppc64,
dwarf_r8_ppc64,
dwarf_r9_ppc64,
dwarf_r10_ppc64,
dwarf_r11_ppc64,
dwarf_r12_ppc64,
dwarf_r13_ppc64,
dwarf_r14_ppc64,
dwarf_r15_ppc64,
dwarf_r16_ppc64,
dwarf_r17_ppc64,
dwarf_r18_ppc64,
dwarf_r19_ppc64,
dwarf_r20_ppc64,
dwarf_r21_ppc64,
dwarf_r22_ppc64,
dwarf_r23_ppc64,
dwarf_r24_ppc64,
dwarf_r25_ppc64,
dwarf_r26_ppc64,
dwarf_r27_ppc64,
dwarf_r28_ppc64,
dwarf_r29_ppc64,
dwarf_r30_ppc64,
dwarf_r31_ppc64,
dwarf_f0_ppc64,
dwarf_f1_ppc64,
dwarf_f2_ppc64,
dwarf_f3_ppc64,
dwarf_f4_ppc64,
dwarf_f5_ppc64,
dwarf_f6_ppc64,
dwarf_f7_ppc64,
dwarf_f8_ppc64,
dwarf_f9_ppc64,
dwarf_f10_ppc64,
dwarf_f11_ppc64,
dwarf_f12_ppc64,
dwarf_f13_ppc64,
dwarf_f14_ppc64,
dwarf_f15_ppc64,
dwarf_f16_ppc64,
dwarf_f17_ppc64,
dwarf_f18_ppc64,
dwarf_f19_ppc64,
dwarf_f20_ppc64,
dwarf_f21_ppc64,
dwarf_f22_ppc64,
dwarf_f23_ppc64,
dwarf_f24_ppc64,
dwarf_f25_ppc64,
dwarf_f26_ppc64,
dwarf_f27_ppc64,
dwarf_f28_ppc64,
dwarf_f29_ppc64,
dwarf_f30_ppc64,
dwarf_f31_ppc64,
dwarf_cr_ppc64 = 64,
dwarf_fpscr_ppc64,
dwarf_msr_ppc64,
dwarf_xer_ppc64 = 100,
dwarf_lr_ppc64 = 108,
dwarf_ctr_ppc64,
dwarf_vscr_ppc64,
dwarf_vrsave_ppc64 = 356,
dwarf_pc_ppc64,
dwarf_vr0_ppc64 = 1124,
dwarf_vr1_ppc64,
dwarf_vr2_ppc64,
dwarf_vr3_ppc64,
dwarf_vr4_ppc64,
dwarf_vr5_ppc64,
dwarf_vr6_ppc64,
dwarf_vr7_ppc64,
dwarf_vr8_ppc64,
dwarf_vr9_ppc64,
dwarf_vr10_ppc64,
dwarf_vr11_ppc64,
dwarf_vr12_ppc64,
dwarf_vr13_ppc64,
dwarf_vr14_ppc64,
dwarf_vr15_ppc64,
dwarf_vr16_ppc64,
dwarf_vr17_ppc64,
dwarf_vr18_ppc64,
dwarf_vr19_ppc64,
dwarf_vr20_ppc64,
dwarf_vr21_ppc64,
dwarf_vr22_ppc64,
dwarf_vr23_ppc64,
dwarf_vr24_ppc64,
dwarf_vr25_ppc64,
dwarf_vr26_ppc64,
dwarf_vr27_ppc64,
dwarf_vr28_ppc64,
dwarf_vr29_ppc64,
dwarf_vr30_ppc64,
dwarf_vr31_ppc64,
};
} // namespace ppc64_dwarf
#endif // utility_PPC64_DWARF_Registers_h_