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[VPlan] Use createSelect in adjustRecipesForReductions (NFCI).
Simplify the code and rename Result->NewExitingVPV as suggested by @ayalz in https://github.com/llvm/llvm-project/pull/70253.
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@@ -167,9 +167,14 @@ public:
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}
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VPValue *createSelect(VPValue *Cond, VPValue *TrueVal, VPValue *FalseVal,
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DebugLoc DL, const Twine &Name = "") {
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return createNaryOp(Instruction::Select, {Cond, TrueVal, FalseVal}, DL,
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Name);
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DebugLoc DL, const Twine &Name = "",
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std::optional<FastMathFlags> FMFs = std::nullopt) {
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auto *Select =
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FMFs ? new VPInstruction(Instruction::Select, {Cond, TrueVal, FalseVal},
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*FMFs, DL, Name)
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: new VPInstruction(Instruction::Select, {Cond, TrueVal, FalseVal},
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DL, Name);
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return tryInsertInstruction(Select);
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}
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/// Create a new ICmp VPInstruction with predicate \p Pred and operands \p A
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@@ -9141,7 +9141,7 @@ void LoopVectorizationPlanner::adjustRecipesForReductions(
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continue;
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const RecurrenceDescriptor &RdxDesc = PhiR->getRecurrenceDescriptor();
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auto *Result = PhiR->getBackedgeValue()->getDefiningRecipe();
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auto *NewExitingVPV = PhiR->getBackedgeValue();
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// If tail is folded by masking, introduce selects between the phi
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// and the live-out instruction of each reduction, at the beginning of the
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// dedicated latch block.
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@@ -9151,21 +9151,20 @@ void LoopVectorizationPlanner::adjustRecipesForReductions(
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VPValue *Red = PhiR->getBackedgeValue();
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assert(Red->getDefiningRecipe()->getParent() != LatchVPBB &&
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"reduction recipe must be defined before latch");
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FastMathFlags FMFs = RdxDesc.getFastMathFlags();
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Type *PhiTy = PhiR->getOperand(0)->getLiveInIRValue()->getType();
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Result =
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std::optional<FastMathFlags> FMFs =
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PhiTy->isFloatingPointTy()
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? new VPInstruction(Instruction::Select, {Cond, Red, PhiR}, FMFs)
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: new VPInstruction(Instruction::Select, {Cond, Red, PhiR});
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Result->insertBefore(&*Builder.getInsertPoint());
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Red->replaceUsesWithIf(
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Result->getVPSingleValue(),
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[](VPUser &U, unsigned) { return isa<VPLiveOut>(&U); });
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? std::make_optional(RdxDesc.getFastMathFlags())
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: std::nullopt;
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NewExitingVPV = Builder.createSelect(Cond, Red, PhiR, {}, "", FMFs);
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Red->replaceUsesWithIf(NewExitingVPV, [](VPUser &U, unsigned) {
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return isa<VPLiveOut>(&U);
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});
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if (PreferPredicatedReductionSelect ||
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TTI.preferPredicatedReductionSelect(
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PhiR->getRecurrenceDescriptor().getOpcode(), PhiTy,
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TargetTransformInfo::ReductionFlags()))
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PhiR->setOperand(1, Result->getVPSingleValue());
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PhiR->setOperand(1, NewExitingVPV);
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}
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// If the vector reduction can be performed in a smaller type, we truncate
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// then extend the loop exit value to enable InstCombine to evaluate the
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@@ -9174,17 +9173,17 @@ void LoopVectorizationPlanner::adjustRecipesForReductions(
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if (MinVF.isVector() && PhiTy != RdxDesc.getRecurrenceType()) {
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assert(!PhiR->isInLoop() && "Unexpected truncated inloop reduction!");
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Type *RdxTy = RdxDesc.getRecurrenceType();
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auto *Trunc = new VPWidenCastRecipe(Instruction::Trunc,
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Result->getVPSingleValue(), RdxTy);
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auto *Trunc =
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new VPWidenCastRecipe(Instruction::Trunc, NewExitingVPV, RdxTy);
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auto *Extnd =
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RdxDesc.isSigned()
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? new VPWidenCastRecipe(Instruction::SExt, Trunc, PhiTy)
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: new VPWidenCastRecipe(Instruction::ZExt, Trunc, PhiTy);
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Trunc->insertAfter(Result);
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Trunc->insertAfter(NewExitingVPV->getDefiningRecipe());
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Extnd->insertAfter(Trunc);
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Result->getVPSingleValue()->replaceAllUsesWith(Extnd);
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Trunc->setOperand(0, Result->getVPSingleValue());
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NewExitingVPV->replaceAllUsesWith(Extnd);
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Trunc->setOperand(0, NewExitingVPV);
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}
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}
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