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Revert "[AArch64] Improve codegen for shifted mask op"

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This reverts commit b4e1466c35.

This causes a crash while building the Linux kernel. See the original
Phabricator review for a reduced C and LLVM IR reproducer.
This commit is contained in:
Nathan Chancellor
2022-11-03 11:33:50 -07:00
parent 5d7fdf67f6
commit 74bace2dfe
2 changed files with 6 additions and 38 deletions
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20
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@@ -14442,23 +14442,15 @@ AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
SDValue ShiftLHS = N->getOperand(0);
EVT VT = N->getValueType(0);
// If ShiftLHS is unsigned bit extraction: ((x >> C) & mask), then do not
// combine it with shift 'N' to let it be lowered to UBFX except:
// ((x >> C) & mask) << C.
// If ShiftLHS is unsigned bit extraction: ((x >> C) & mask), then do not combine
// it with shift 'N' to let it be lowered to UBFX.
if (ShiftLHS.getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
isa<ConstantSDNode>(ShiftLHS.getOperand(1))) {
uint64_t TruncMask = ShiftLHS.getConstantOperandVal(1);
if (isMask_64(TruncMask)) {
SDValue AndLHS = ShiftLHS.getOperand(0);
if (AndLHS.getOpcode() == ISD::SRL) {
if (auto *SRLC = dyn_cast<ConstantSDNode>(AndLHS.getOperand(1))) {
if (N->getOpcode() == ISD::SHL)
if (auto *SHLC = dyn_cast<ConstantSDNode>(N->getOperand(1)))
return SRLC->getAPIntValue() == SHLC->getAPIntValue();
return false;
}
}
}
if (isMask_64(TruncMask) &&
ShiftLHS.getOperand(0).getOpcode() == ISD::SRL &&
isa<ConstantSDNode>(ShiftLHS.getOperand(0).getOperand(1)))
return false;
}
return true;
}

24
llvm/test/CodeGen/AArch64/shift-logic.ll
View File

@@ -151,27 +151,3 @@ define i32 @lshr_or_extra_use(i32 %x, i32 %y, i32* %p) nounwind {
%sh1 = lshr i32 %r, 7
ret i32 %sh1
}
define i64 @desirable_to_commute1(i64 %x) {
; CHECK-LABEL: desirable_to_commute1:
; CHECK: // %bb.0:
; CHECK-NEXT: and x0, x0, #0x7fff8
; CHECK-NEXT: ret
%s1 = lshr i64 %x, 3
%a = and i64 %s1, 65535
%s2 = shl i64 %a, 3
ret i64 %s2
}
define i64 @desirable_to_commute2(i64* %p, i64 %i) {
; CHECK-LABEL: desirable_to_commute2:
; CHECK: // %bb.0:
; CHECK-NEXT: and x8, x1, #0x1ff8
; CHECK-NEXT: ldr x0, [x0, x8]
; CHECK-NEXT: ret
%lshr = lshr i64 %i, 3
%and = and i64 %lshr, 1023
%pidx = getelementptr i64, i64* %p, i64 %and
%r = load i64, i64* %pidx
ret i64 %r
}