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[UpdateTestChecks] Sync flags in update_mir_test_checks.py with MIFlags

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Some instructions are not matched by update_mir_test_checks.py because MIFlags and
regex in the script are not synchronized.

Differential Revision: https://reviews.llvm.org/D136170
This commit is contained in:
Anton Sidorenko
2022-10-18 16:35:19 +03:00
parent 2e5bf4da99
commit 7bc7f2da76
2 changed files with 3 additions and 3 deletions
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4
llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir.expected
View File

@@ -73,8 +73,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
; CHECK-NEXT: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load (s32) from constant-pool)
; CHECK-NEXT: %2:fr32 = nsz nofpexcept DIVSSrr [[MOVSSrm_alt]], [[COPY]], implicit $mxcsr
; CHECK-NEXT: $xmm0 = COPY %2
; CHECK-NEXT: [[DIVSSrr:%[0-9]+]]:fr32 = nsz nofpexcept DIVSSrr [[MOVSSrm_alt]], [[COPY]], implicit $mxcsr
; CHECK-NEXT: $xmm0 = COPY [[DIVSSrr]]
; CHECK-NEXT: RET 0, $xmm0
%0:fr32 = COPY $xmm0
%1:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load (s32) from constant-pool)

2
llvm/utils/update_mir_test_checks.py
View File

@@ -35,7 +35,7 @@ MIR_BASIC_BLOCK_RE = re.compile(r' *bb\.[0-9]+.*:$')
VREG_RE = re.compile(r'(%[0-9]+)(?::[a-z0-9_]+)?(?:\([<>a-z0-9 ]+\))?')
MI_FLAGS_STR= (
r'(frame-setup |frame-destroy |nnan |ninf |nsz |arcp |contract |afn '
r'|reassoc |nuw |nsw |exact |fpexcept )*')
r'|reassoc |nuw |nsw |exact |nofpexcept |nomerge )*')
VREG_DEF_RE = re.compile(
r'^ *(?P<vregs>{0}(?:, {0})*) = '
r'{1}(?P<opcode>[A-Zt][A-Za-z0-9_]+)'.format(VREG_RE.pattern, MI_FLAGS_STR))