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[RISCV] Swap rs1 and rs2 names in TH_ADDSL patterns. NFC

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The names should match the operand order of the final instruction.
I assume these patterns were somewhat copied from Zba where rs1 is
shifted, but for th.addsl, rs2 is shifted.
This commit is contained in:
Craig Topper
2024-12-29 12:44:30 -08:00
parent c557ce9f27
commit 82ffdf317e
1 changed files with 8 additions and 8 deletions
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16
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
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@@ -538,16 +538,16 @@ multiclass VPatTernaryVMAQA_VV_VX<string intrinsic, string instruction,
let Predicates = [HasVendorXTHeadBa] in {
def : Pat<(add_like_non_imm12 (shl GPR:$rs2, uimm2:$uimm2), (XLenVT GPR:$rs1)),
(TH_ADDSL GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
def : Pat<(XLenVT (riscv_shl_add GPR:$rs1, uimm2:$uimm2, GPR:$rs2)),
(TH_ADDSL GPR:$rs2, GPR:$rs1, uimm2:$uimm2)>;
def : Pat<(XLenVT (riscv_shl_add GPR:$rs2, uimm2:$uimm2, GPR:$rs1)),
(TH_ADDSL GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
// Reuse complex patterns from StdExtZba
def : Pat<(add_like_non_imm12 sh1add_op:$rs1, (XLenVT GPR:$rs2)),
(TH_ADDSL GPR:$rs2, sh1add_op:$rs1, 1)>;
def : Pat<(add_like_non_imm12 sh2add_op:$rs1, (XLenVT GPR:$rs2)),
(TH_ADDSL GPR:$rs2, sh2add_op:$rs1, 2)>;
def : Pat<(add_like_non_imm12 sh3add_op:$rs1, (XLenVT GPR:$rs2)),
(TH_ADDSL GPR:$rs2, sh3add_op:$rs1, 3)>;
def : Pat<(add_like_non_imm12 sh1add_op:$rs2, (XLenVT GPR:$rs1)),
(TH_ADDSL GPR:$rs1, sh1add_op:$rs2, 1)>;
def : Pat<(add_like_non_imm12 sh2add_op:$rs2, (XLenVT GPR:$rs1)),
(TH_ADDSL GPR:$rs1, sh2add_op:$rs2, 2)>;
def : Pat<(add_like_non_imm12 sh3add_op:$rs2, (XLenVT GPR:$rs1)),
(TH_ADDSL GPR:$rs1, sh3add_op:$rs2, 3)>;
def : Pat<(add_like (XLenVT GPR:$r), CSImm12MulBy4:$i),
(TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), CSImm12MulBy4:$i)), 2)>;