mirror of
https://github.com/intel/llvm.git
synced 2026-01-16 05:32:28 +08:00
Reformat the emulation test data files.
llvm-svn: 129991
This commit is contained in:
111
lldb/test/arm_emulation/new-test-files/test-add-1-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-1-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r0, r0, r15"
|
||||
triple=arm-apple-darwin
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||||
opcode=0xe080000f
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
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||||
}
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||||
}
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||||
after_state={
|
||||
registers={
|
||||
r0=0x00003000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
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||||
}
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||||
}
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||||
111
lldb/test/arm_emulation/new-test-files/test-add-1-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-1-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r0, r13, #0"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xa800
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-10-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-10-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add sp, r13"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x44ed
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x5fbffca0
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-11-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-11-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add sp, r15"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x44fd
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fe02e50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-12-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-12-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add sp, r8"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x44c5
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-2-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-2-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r0, r13, #0"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe28d0000
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe58
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-2-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-2-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r0, sp, r0"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4468
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-3-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-3-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r0, r1, r0, lsl #2"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe0810100
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe48
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000001
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe48
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-3-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-3-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add.w r10, r13, #31"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xf10d0a1f
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe40
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe40
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe40
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x2fdffe5f
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe40
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-4-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-4-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r0, r2, r7, lsl r1"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe0820117
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe40
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe40
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x5fbffc82
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe40
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe40
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-4-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-4-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r3, r13, #16"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xab04
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe48
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x2fdffe58
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe48
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-5-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-5-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r10, r13, #31"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe28da01f
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x2fdffe6f
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-5-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-5-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r3, sp, r3"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x446b
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x2fdffe53
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-6-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-6-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r12, r13, #24"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe28dc018
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x2fdffe68
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-6-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-6-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r5, r13, #32"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xad08
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe48
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x2fdffe68
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe48
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-7-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-7-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add r6, sp, #8"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe28d6008
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x2fdffe68
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-7-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-7-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add sp, #16"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xb004
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe68
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-8-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-8-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add sp, r8"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe08dd008
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe68
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-8-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-8-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add sp, #4"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xb001
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe5c
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-add-9-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-add-9-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="add sp, r10"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x44d5
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe5a
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-bic-1-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-bic-1-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="bic r4, r9"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe1c44009
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-bic-1-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-bic-1-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="bics r4, r6"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x43b4
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000000
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
119
lldb/test/arm_emulation/new-test-files/test-ldmia-1-arm.dat
Normal file
119
lldb/test/arm_emulation/new-test-files/test-ldmia-1-arm.dat
Normal file
@@ -0,0 +1,119 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldmia r0!, {r1, r3}"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe8b0000a
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe50
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x0
|
||||
0x2e7c
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe58
|
||||
r1=0x00000000
|
||||
r2=0x2fdffe70
|
||||
r3=0x00002e7c
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
119
lldb/test/arm_emulation/new-test-files/test-ldmia-1-thumb.dat
Normal file
119
lldb/test/arm_emulation/new-test-files/test-ldmia-1-thumb.dat
Normal file
@@ -0,0 +1,119 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldmia r0!, {r1, r3}"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xc80a
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe40
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x0
|
||||
0x2f84
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe40
|
||||
r1=0x2fdffe50
|
||||
r2=0x2fdffe60
|
||||
r3=0x2fdffe70
|
||||
r4=0x2fdffe80
|
||||
r5=0x2fdffe90
|
||||
r6=0x2fdffea0
|
||||
r7=0x2fdffe40
|
||||
r8=0x2fdffec0
|
||||
r9=0x2fdffed0
|
||||
r10=0x2fdffee0
|
||||
r11=0x2fdffef0
|
||||
r12=0x2fdfff00
|
||||
r13=0x2fdffe40
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe48
|
||||
r1=0x00000000
|
||||
r2=0x2fdffe60
|
||||
r3=0x00002f84
|
||||
r4=0x2fdffe80
|
||||
r5=0x2fdffe90
|
||||
r6=0x2fdffea0
|
||||
r7=0x2fdffe40
|
||||
r8=0x2fdffec0
|
||||
r9=0x2fdffed0
|
||||
r10=0x2fdffee0
|
||||
r11=0x2fdffef0
|
||||
r12=0x2fdfff00
|
||||
r13=0x2fdffe40
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
123
lldb/test/arm_emulation/new-test-files/test-ldmia-2-arm.dat
Normal file
123
lldb/test/arm_emulation/new-test-files/test-ldmia-2-arm.dat
Normal file
@@ -0,0 +1,123 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldmia r0!, {r2, r4, r6, r8, r10, r12}"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe8b01554
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe20
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x0
|
||||
0x2e7c
|
||||
0x1
|
||||
0x2fdffe84
|
||||
0x0
|
||||
0x0
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe20
|
||||
r1=0x2fdffe30
|
||||
r2=0x2fdffe40
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe60
|
||||
r5=0x2fdffe70
|
||||
r6=0x2fdffe80
|
||||
r7=0x2fdffe20
|
||||
r8=0x2fdffea0
|
||||
r9=0x2fdffeb0
|
||||
r10=0x2fdffec0
|
||||
r11=0x2fdffed0
|
||||
r12=0x2fdffee0
|
||||
r13=0x2fdffe20
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe38
|
||||
r1=0x2fdffe30
|
||||
r2=0x00000000
|
||||
r3=0x0000001f
|
||||
r4=0x00002e7c
|
||||
r5=0x2fdffe70
|
||||
r6=0x00000001
|
||||
r7=0x2fdffe20
|
||||
r8=0x2fdffe84
|
||||
r9=0x2fdffeb0
|
||||
r10=0x00000000
|
||||
r11=0x2fdffed0
|
||||
r12=0x00000000
|
||||
r13=0x2fdffe20
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
123
lldb/test/arm_emulation/new-test-files/test-ldmia-2-thumb.dat
Normal file
123
lldb/test/arm_emulation/new-test-files/test-ldmia-2-thumb.dat
Normal file
@@ -0,0 +1,123 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldmia.w r0!,{r2,r4,r6,r8,r10,r12}"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xe8b01554
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe50
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x0
|
||||
0x2f80
|
||||
0x1
|
||||
0x2fdffeac
|
||||
0x0
|
||||
0x0
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe68
|
||||
r1=0x2fdffe60
|
||||
r2=0x00000000
|
||||
r3=0x2fdffe80
|
||||
r4=0x00002f80
|
||||
r5=0x2fdffea0
|
||||
r6=0x00000001
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffeac
|
||||
r9=0x2fdffee0
|
||||
r10=0x00000000
|
||||
r11=0x2fdfff00
|
||||
r12=0x00000000
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
119
lldb/test/arm_emulation/new-test-files/test-ldmia-3-arm.dat
Normal file
119
lldb/test/arm_emulation/new-test-files/test-ldmia-3-arm.dat
Normal file
@@ -0,0 +1,119 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldmia r14!, {r1, r3}"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe8be000a
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2e7c
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0xe59fc00c
|
||||
0xe08fc00c
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0xe59fc00c
|
||||
r2=0x2fdffe70
|
||||
r3=0xe08fc00c
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
119
lldb/test/arm_emulation/new-test-files/test-ldmia-3-thumb.dat
Normal file
119
lldb/test/arm_emulation/new-test-files/test-ldmia-3-thumb.dat
Normal file
@@ -0,0 +1,119 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldmia.w r14!, {r1, r3}"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xe8be000a
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2f80
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0xe59fc00c
|
||||
0xe08fc00c
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe78
|
||||
r1=0x2fdffe88
|
||||
r2=0x2fdffe98
|
||||
r3=0x2fdffea8
|
||||
r4=0x2fdffeb8
|
||||
r5=0x2fdffec8
|
||||
r6=0x2fdffed8
|
||||
r7=0x2fdffe78
|
||||
r8=0x2fdffef8
|
||||
r9=0x2fdfff08
|
||||
r10=0x2fdfff18
|
||||
r11=0x2fdfff28
|
||||
r12=0x2fdfff38
|
||||
r13=0x2fdffe78
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe78
|
||||
r1=0xe59fc00c
|
||||
r2=0x2fdffe98
|
||||
r3=0xe08fc00c
|
||||
r4=0x2fdffeb8
|
||||
r5=0x2fdffec8
|
||||
r6=0x2fdffed8
|
||||
r7=0x2fdffe78
|
||||
r8=0x2fdffef8
|
||||
r9=0x2fdfff08
|
||||
r10=0x2fdfff18
|
||||
r11=0x2fdfff28
|
||||
r12=0x2fdfff38
|
||||
r13=0x2fdffe78
|
||||
r14=0x00002f88
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-1-arm.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-1-arm.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r0, [pc, #+24]"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe59f0018
|
||||
before_state={
|
||||
memory={
|
||||
address=0x3018
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x3030
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00003030
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-1-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-1-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r0, [pc, #12]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4803
|
||||
before_state={
|
||||
memory={
|
||||
address=0x300c
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x3024
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00003024
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-10-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-10-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr.w r10,[ pc, #4]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xf8dfa004
|
||||
before_state={
|
||||
memory={
|
||||
address=0x3000
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x2fe01000
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe48
|
||||
r1=0x2fdffe58
|
||||
r2=0x2fdffe68
|
||||
r3=0x2fdffe78
|
||||
r4=0x2fdffe88
|
||||
r5=0x2fdffe98
|
||||
r6=0x2fdffea8
|
||||
r7=0x2fdffe48
|
||||
r8=0x2fdffec8
|
||||
r9=0x2fdffed8
|
||||
r10=0x2fdffee8
|
||||
r11=0x2fdffef8
|
||||
r12=0x2fdfff08
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe48
|
||||
r1=0x2fdffe58
|
||||
r2=0x2fdffe68
|
||||
r3=0x2fdffe78
|
||||
r4=0x2fdffe88
|
||||
r5=0x2fdffe98
|
||||
r6=0x2fdffea8
|
||||
r7=0x2fdffe48
|
||||
r8=0x2fdffec8
|
||||
r9=0x2fdffed8
|
||||
r10=0x2fe01000
|
||||
r11=0x2fdffef8
|
||||
r12=0x2fdfff08
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-11-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-11-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr.w r8, [pc , #0]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xf8df8000
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2ffc
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0xa0e1defe
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0xa0e1defe
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-12-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-12-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr.w r9, [pc, #-4]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xf85f9004
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fec
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x9004f85f
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x9004f85f
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-2-arm.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-2-arm.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r0, [pc, #256]"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe59f0100
|
||||
before_state={
|
||||
memory={
|
||||
address=0x3100
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x0
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-2-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-2-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r0, [pc, #+24]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4806
|
||||
before_state={
|
||||
memory={
|
||||
address=0x3018
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x3030
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00003030
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-3-arm.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-3-arm.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r0, [r13, #+24]"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe59d0018
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe70
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x2fdffe80
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe80
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-3-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-3-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r0, [pc, #256]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4840
|
||||
before_state={
|
||||
memory={
|
||||
address=0x3100
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x0
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe48
|
||||
r1=0x2fdffe58
|
||||
r2=0x2fdffe68
|
||||
r3=0x2fdffe78
|
||||
r4=0x2fdffe88
|
||||
r5=0x2fdffe98
|
||||
r6=0x2fdffea8
|
||||
r7=0x2fdffe48
|
||||
r8=0x2fdffec8
|
||||
r9=0x2fdffed8
|
||||
r10=0x2fdffee8
|
||||
r11=0x2fdffef8
|
||||
r12=0x2fdfff08
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x2fdffe58
|
||||
r2=0x2fdffe68
|
||||
r3=0x2fdffe78
|
||||
r4=0x2fdffe88
|
||||
r5=0x2fdffe98
|
||||
r6=0x2fdffea8
|
||||
r7=0x2fdffe48
|
||||
r8=0x2fdffec8
|
||||
r9=0x2fdffed8
|
||||
r10=0x2fdffee8
|
||||
r11=0x2fdffef8
|
||||
r12=0x2fdfff08
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-4-arm.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-4-arm.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r1, [r5, #16]"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe5951010
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffeb8
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x7365742d
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe58
|
||||
r1=0x2fdffe68
|
||||
r2=0x2fdffe78
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe98
|
||||
r5=0x2fdffea8
|
||||
r6=0x2fdffeb8
|
||||
r7=0x2fdffe58
|
||||
r8=0x2fdffed8
|
||||
r9=0x2fdffee8
|
||||
r10=0x2fdffef8
|
||||
r11=0x2fdfff08
|
||||
r12=0x2fdfff18
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe58
|
||||
r1=0x7365742d
|
||||
r2=0x2fdffe78
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe98
|
||||
r5=0x2fdffea8
|
||||
r6=0x2fdffeb8
|
||||
r7=0x2fdffe58
|
||||
r8=0x2fdffed8
|
||||
r9=0x2fdffee8
|
||||
r10=0x2fdffef8
|
||||
r11=0x2fdfff08
|
||||
r12=0x2fdfff18
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-4-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-4-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r0, [r13, #+24]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x9806
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe60
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x2fdffe70
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe48
|
||||
r1=0x2fdffe58
|
||||
r2=0x2fdffe68
|
||||
r3=0x2fdffe78
|
||||
r4=0x2fdffe88
|
||||
r5=0x2fdffe98
|
||||
r6=0x2fdffea8
|
||||
r7=0x2fdffe48
|
||||
r8=0x2fdffec8
|
||||
r9=0x2fdffed8
|
||||
r10=0x2fdffee8
|
||||
r11=0x2fdffef8
|
||||
r12=0x2fdfff08
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe70
|
||||
r1=0x2fdffe58
|
||||
r2=0x2fdffe68
|
||||
r3=0x2fdffe78
|
||||
r4=0x2fdffe88
|
||||
r5=0x2fdffe98
|
||||
r6=0x2fdffea8
|
||||
r7=0x2fdffe48
|
||||
r8=0x2fdffec8
|
||||
r9=0x2fdffed8
|
||||
r10=0x2fdffee8
|
||||
r11=0x2fdffef8
|
||||
r12=0x2fdfff08
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-5-arm.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-5-arm.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r2, [r0]"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe5902000
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe60
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x0
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe60
|
||||
r1=0x2fdffe70
|
||||
r2=0x2fdffe80
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffea0
|
||||
r5=0x2fdffeb0
|
||||
r6=0x2fdffec0
|
||||
r7=0x2fdffe60
|
||||
r8=0x2fdffee0
|
||||
r9=0x2fdffef0
|
||||
r10=0x2fdfff00
|
||||
r11=0x2fdfff10
|
||||
r12=0x2fdfff20
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe60
|
||||
r1=0x2fdffe70
|
||||
r2=0x00000000
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffea0
|
||||
r5=0x2fdffeb0
|
||||
r6=0x2fdffec0
|
||||
r7=0x2fdffe60
|
||||
r8=0x2fdffee0
|
||||
r9=0x2fdffef0
|
||||
r10=0x2fdfff00
|
||||
r11=0x2fdfff10
|
||||
r12=0x2fdfff20
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-5-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-5-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r1, [pc, #0]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4900
|
||||
before_state={
|
||||
memory={
|
||||
address=0x3000
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x2fe01000
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fe01000
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-6-arm.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-6-arm.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r2, [r6], +r8, lsl #2"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe6962108
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffea8
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x7365742d
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe48
|
||||
r1=0x2fdffe58
|
||||
r2=0x2fdffe68
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe88
|
||||
r5=0x2fdffe98
|
||||
r6=0x2fdffea8
|
||||
r7=0x2fdffe48
|
||||
r8=0x2fdffec8
|
||||
r9=0x2fdffed8
|
||||
r10=0x2fdffee8
|
||||
r11=0x2fdffef8
|
||||
r12=0x2fdfff08
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe48
|
||||
r1=0x2fdffe58
|
||||
r2=0x7365742d
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe88
|
||||
r5=0x2fdffe98
|
||||
r6=0xef5ff9c8
|
||||
r7=0x2fdffe48
|
||||
r8=0x2fdffec8
|
||||
r9=0x2fdffed8
|
||||
r10=0x2fdffee8
|
||||
r11=0x2fdffef8
|
||||
r12=0x2fdfff08
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-6-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-6-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r1, [r5, #16]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x6929
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffeb0
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x65742d62
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x65742d62
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-7-arm.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-7-arm.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r2, [sp, #24]"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe59d2018
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe70
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x0
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000000
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-7-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-7-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r2, [r0]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x6802
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe58
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x0
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe58
|
||||
r1=0x2fdffe68
|
||||
r2=0x2fdffe78
|
||||
r3=0x2fdffe88
|
||||
r4=0x2fdffe98
|
||||
r5=0x2fdffea8
|
||||
r6=0x2fdffeb8
|
||||
r7=0x2fdffe58
|
||||
r8=0x2fdffed8
|
||||
r9=0x2fdffee8
|
||||
r10=0x2fdffef8
|
||||
r11=0x2fdfff08
|
||||
r12=0x2fdfff18
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe58
|
||||
r1=0x2fdffe68
|
||||
r2=0x00000000
|
||||
r3=0x2fdffe88
|
||||
r4=0x2fdffe98
|
||||
r5=0x2fdffea8
|
||||
r6=0x2fdffeb8
|
||||
r7=0x2fdffe58
|
||||
r8=0x2fdffed8
|
||||
r9=0x2fdffee8
|
||||
r10=0x2fdffef8
|
||||
r11=0x2fdfff08
|
||||
r12=0x2fdfff18
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-8-arm.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-8-arm.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r3, [r11, #-8]"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe51b3008
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdfff00
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x63387830
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe58
|
||||
r1=0x2fdffe68
|
||||
r2=0x2fdffe78
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe98
|
||||
r5=0x2fdffea8
|
||||
r6=0x2fdffeb8
|
||||
r7=0x2fdffe58
|
||||
r8=0x2fdffed8
|
||||
r9=0x2fdffee8
|
||||
r10=0x2fdffef8
|
||||
r11=0x2fdfff08
|
||||
r12=0x2fdfff18
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe58
|
||||
r1=0x2fdffe68
|
||||
r2=0x2fdffe78
|
||||
r3=0x63387830
|
||||
r4=0x2fdffe98
|
||||
r5=0x2fdffea8
|
||||
r6=0x2fdffeb8
|
||||
r7=0x2fdffe58
|
||||
r8=0x2fdffed8
|
||||
r9=0x2fdffee8
|
||||
r10=0x2fdffef8
|
||||
r11=0x2fdfff08
|
||||
r12=0x2fdfff18
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-8-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-8-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr r2, [sp, #24]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x9a06
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe68
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x2fdffe78
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe78
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldr-9-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldr-9-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldr.w r3, [r11, #8]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xf8db3008
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdfff08
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x62343134
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x2fdffe80
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x62343134
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
119
lldb/test/arm_emulation/new-test-files/test-ldrd-1-arm.dat
Normal file
119
lldb/test/arm_emulation/new-test-files/test-ldrd-1-arm.dat
Normal file
@@ -0,0 +1,119 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldrd r0, r1, [r12, #+4]"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe1cc00d4
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdfff14
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x30313038
|
||||
0x31623039
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x30313038
|
||||
r1=0x31623039
|
||||
r2=0x2fdffe70
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
119
lldb/test/arm_emulation/new-test-files/test-ldrd-1-thumb.dat
Normal file
119
lldb/test/arm_emulation/new-test-files/test-ldrd-1-thumb.dat
Normal file
@@ -0,0 +1,119 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldrd r0, r1, [r12, #+4]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xe9dc0101
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdfff3c
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x0
|
||||
0x0
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe78
|
||||
r1=0x2fdffe88
|
||||
r2=0x2fdffe98
|
||||
r3=0x2fdffea8
|
||||
r4=0x2fdffeb8
|
||||
r5=0x2fdffec8
|
||||
r6=0x2fdffed8
|
||||
r7=0x2fdffe78
|
||||
r8=0x2fdffef8
|
||||
r9=0x2fdfff08
|
||||
r10=0x2fdfff18
|
||||
r11=0x2fdfff28
|
||||
r12=0x2fdfff38
|
||||
r13=0x2fdffe78
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000000
|
||||
r2=0x2fdffe98
|
||||
r3=0x2fdffea8
|
||||
r4=0x2fdffeb8
|
||||
r5=0x2fdffec8
|
||||
r6=0x2fdffed8
|
||||
r7=0x2fdffe78
|
||||
r8=0x2fdffef8
|
||||
r9=0x2fdfff08
|
||||
r10=0x2fdfff18
|
||||
r11=0x2fdfff28
|
||||
r12=0x2fdfff38
|
||||
r13=0x2fdffe78
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
119
lldb/test/arm_emulation/new-test-files/test-ldrd-2-thumb.dat
Normal file
119
lldb/test/arm_emulation/new-test-files/test-ldrd-2-thumb.dat
Normal file
@@ -0,0 +1,119 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldrd r4, r5, [pc, #-0]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xe9df4500
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2ffc
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0xa0e1defe
|
||||
0x2fe01000
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe78
|
||||
r1=0x2fdffe88
|
||||
r2=0x2fdffe98
|
||||
r3=0x2fdffea8
|
||||
r4=0x2fdffeb8
|
||||
r5=0x2fdffec8
|
||||
r6=0x2fdffed8
|
||||
r7=0x2fdffe78
|
||||
r8=0x2fdffef8
|
||||
r9=0x2fdfff08
|
||||
r10=0x2fdfff18
|
||||
r11=0x2fdfff28
|
||||
r12=0x2fdfff38
|
||||
r13=0x2fdffe78
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe78
|
||||
r1=0x2fdffe88
|
||||
r2=0x2fdffe98
|
||||
r3=0x2fdffea8
|
||||
r4=0xa0e1defe
|
||||
r5=0x2fe01000
|
||||
r6=0x2fdffed8
|
||||
r7=0x2fdffe78
|
||||
r8=0x2fdffef8
|
||||
r9=0x2fdfff08
|
||||
r10=0x2fdfff18
|
||||
r11=0x2fdfff28
|
||||
r12=0x2fdfff38
|
||||
r13=0x2fdffe78
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldrh-1-thumb.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldrh-1-thumb.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldrh r0, [r2, #16]"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x8a10
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe78
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0x762f
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe48
|
||||
r1=0x2fdffe58
|
||||
r2=0x2fdffe68
|
||||
r3=0x2fdffe78
|
||||
r4=0x2fdffe88
|
||||
r5=0x2fdffe98
|
||||
r6=0x2fdffea8
|
||||
r7=0x2fdffe48
|
||||
r8=0x2fdffec8
|
||||
r9=0x2fdffed8
|
||||
r10=0x2fdffee8
|
||||
r11=0x2fdffef8
|
||||
r12=0x2fdfff08
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x0000762f
|
||||
r1=0x2fdffe58
|
||||
r2=0x2fdffe68
|
||||
r3=0x2fdffe78
|
||||
r4=0x2fdffe88
|
||||
r5=0x2fdffe98
|
||||
r6=0x2fdffea8
|
||||
r7=0x2fdffe48
|
||||
r8=0x2fdffec8
|
||||
r9=0x2fdffed8
|
||||
r10=0x2fdffee8
|
||||
r11=0x2fdffef8
|
||||
r12=0x2fdfff08
|
||||
r13=0x2fdffe48
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldrsh-1-arm.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldrsh-1-arm.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldrsh r0, [r2], #+15"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe0d200ff
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe70
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0xfffffeeb
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0xfffffeeb
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe7f
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
118
lldb/test/arm_emulation/new-test-files/test-ldrsh-2-arm.dat
Normal file
118
lldb/test/arm_emulation/new-test-files/test-ldrsh-2-arm.dat
Normal file
@@ -0,0 +1,118 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="ldrsh r14, [r2], #+15"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe0d2e0ff
|
||||
before_state={
|
||||
memory={
|
||||
address=0x2fdffe70
|
||||
data_encoding=uint32_t
|
||||
data=[
|
||||
0xfffffeec
|
||||
]
|
||||
}
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe70
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe50
|
||||
r1=0x2fdffe60
|
||||
r2=0x2fdffe7f
|
||||
r3=0x0000001f
|
||||
r4=0x2fdffe90
|
||||
r5=0x2fdffea0
|
||||
r6=0x2fdffeb0
|
||||
r7=0x2fdffe50
|
||||
r8=0x2fdffed0
|
||||
r9=0x2fdffee0
|
||||
r10=0x2fdffef0
|
||||
r11=0x2fdfff00
|
||||
r12=0x2fdfff10
|
||||
r13=0x2fdffe50
|
||||
r14=0xfffffeec
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-1-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-1-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r12, #256"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe3a0cc01
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x00000100
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-1-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-1-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov ip, pc"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46fc
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x00003000
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-10-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-10-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r0, r15"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4678
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00003000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-11-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-11-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r0, r7"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4638
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x2fdffe58
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-12-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-12-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov.w r12, #256"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xf44f7c80
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x00000100
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-13-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-13-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r12, r13"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46ec
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x2fdffe50
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-14-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-14-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r14, r2"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4696
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00000002
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-15-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-15-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r1, r14"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4671
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00002f84
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-16-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-16-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r2, ip"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4662
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x0000000c
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-17-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-17-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r2, r13"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x466a
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x2fdffe50
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-18-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-18-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r2, r9"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x464a
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000009
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-19-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-19-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r3, r12"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4663
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000000c
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-2-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-2-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r12, r13"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe1a0c00d
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x2fdffe58
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-2-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-2-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov ip, r8"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46c4
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x00000008
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-20-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-20-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r3, r13"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x466b
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x2fdffe50
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-21-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-21-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r3, sp"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x466b
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x2fdffe58
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-22-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-22-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r4, r11"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x465c
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x0000000b
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-23-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-23-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r5, r10"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4655
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x0000000a
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe50
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe50
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-24-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-24-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r6, r9"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x464e
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000009
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-25-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-25-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r7, lr"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4677
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x00002f84
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-26-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-26-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r7, r8"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4647
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x00000008
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-27-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-27-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r9, pc"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46f9
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00003000
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-28-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-28-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov sp, ip"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46e5
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x0000000c
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-29-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-29-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov sp, pc"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46fd
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x00003000
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-3-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-3-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r14, r2"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe1a0e002
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00000002
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-3-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-3-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov ip, sp"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46ec
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x2fdffe58
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-30-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-30-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov sp, r7"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46bd
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-31-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-31-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="movs r3, #1"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x2301
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000001
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffe
|
||||
cpsr=0x20000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-4-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-4-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r2, r9"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe1a02009
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000009
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-4-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-4-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov lr, pc"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46fe
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00003000
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-5-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-5-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r3, #2147483648"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe3a03102
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe38
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe38
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x80000000
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe38
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe38
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-5-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-5-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov lr, r2"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x4696
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00000002
|
||||
r15=0x00002ffe
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-6-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-6-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov r3, r13"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe1a0300d
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x2fdffe60
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-6-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-6-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov pc, ip"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46e7
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x0000000c
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-7-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-7-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov pc, lr"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46f7
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002f84
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-8-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-8-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov pc, r4"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46a7
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00000004
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mov-9-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mov-9-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mov pc, sp"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0x46ef
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002f84
|
||||
r15=0x2fdffe58
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-moveq-1-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-moveq-1-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="moveq r3, #1"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0x3a03001
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000001
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-movs-1-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-movs-1-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="movs r12, r13"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe1b0c00d
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe58
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x2fdffe58
|
||||
r13=0x2fdffe58
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x20000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mvn-1-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mvn-1-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mvn r14, #1"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe3e0e001
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0xfffffffe
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mvn-1-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mvn-1-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mvn r0, #1"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xf06f0001
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe98
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe98
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0xfffffffe
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe98
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe98
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mvn-2-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mvn-2-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mvn r0, #1"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe3e00001
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe68
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe68
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0xfffffffe
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe68
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe68
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mvn-2-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mvn-2-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mvn r0, #31"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xf06f001f
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe90
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe90
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0xffffffe0
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe90
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe90
|
||||
r14=0x00002f80
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mvn-3-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mvn-3-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mvn r0, #31"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe3e0001f
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0xffffffe0
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mvn-3-thumb.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mvn-3-thumb.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mvn r14, #1"
|
||||
triple=thumb-apple-darwin
|
||||
opcode=0xf06f0e01
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe90
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe90
|
||||
r14=0x00002f80
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x00000003
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe90
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe90
|
||||
r14=0xfffffffe
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000030
|
||||
s0=0x00000000
|
||||
s1=0x00000000
|
||||
s2=0x00000000
|
||||
s3=0x00000000
|
||||
s4=0x00000000
|
||||
s5=0x00000000
|
||||
s6=0x00000000
|
||||
s7=0x00000000
|
||||
s8=0x00000000
|
||||
s9=0x00000000
|
||||
s10=0x00000000
|
||||
s11=0x00000000
|
||||
s12=0x00000000
|
||||
s13=0x00000000
|
||||
s14=0x00000000
|
||||
s15=0x00000000
|
||||
s16=0x00000000
|
||||
s17=0x00000000
|
||||
s18=0x00000000
|
||||
s19=0x00000000
|
||||
s20=0x00000000
|
||||
s21=0x00000000
|
||||
s22=0x00000000
|
||||
s23=0x00000000
|
||||
s24=0x00000000
|
||||
s25=0x00000000
|
||||
s26=0x00000000
|
||||
s27=0x00000000
|
||||
s28=0x00000000
|
||||
s29=0x00000000
|
||||
s30=0x00000000
|
||||
s31=0x00000000
|
||||
}
|
||||
}
|
||||
}
|
||||
111
lldb/test/arm_emulation/new-test-files/test-mvn-4-arm.dat
Normal file
111
lldb/test/arm_emulation/new-test-files/test-mvn-4-arm.dat
Normal file
@@ -0,0 +1,111 @@
|
||||
InstructionEmulationState={
|
||||
assembly_string="mvn r3, r8"
|
||||
triple=arm-apple-darwin
|
||||
opcode=0xe1e03008
|
||||
before_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0x0000001f
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ff8
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
after_state={
|
||||
registers={
|
||||
r0=0x00000000
|
||||
r1=0x00000001
|
||||
r2=0x00000002
|
||||
r3=0xfffffff7
|
||||
r4=0x00000004
|
||||
r5=0x00000005
|
||||
r6=0x00000006
|
||||
r7=0x2fdffe60
|
||||
r8=0x00000008
|
||||
r9=0x00000009
|
||||
r10=0x0000000a
|
||||
r11=0x0000000b
|
||||
r12=0x0000000c
|
||||
r13=0x2fdffe60
|
||||
r14=0x00002e7c
|
||||
r15=0x00002ffc
|
||||
cpsr=0x60000010
|
||||
s0=0x00000000
|
||||
s1=0x00000001
|
||||
s2=0x00000002
|
||||
s3=0x00000003
|
||||
s4=0x00000004
|
||||
s5=0x00000005
|
||||
s6=0x00000006
|
||||
s7=0x00000007
|
||||
s8=0x00000008
|
||||
s9=0x00000009
|
||||
s10=0x0000000a
|
||||
s11=0x0000000b
|
||||
s12=0x0000000c
|
||||
s13=0x0000000d
|
||||
s14=0x0000000e
|
||||
s15=0x0000000f
|
||||
s16=0x00000010
|
||||
s17=0x00000011
|
||||
s18=0x00000012
|
||||
s19=0x00000013
|
||||
s20=0x00000014
|
||||
s21=0x00000015
|
||||
s22=0x00000016
|
||||
s23=0x00000017
|
||||
s24=0x00000018
|
||||
s25=0x00000019
|
||||
s26=0x0000001a
|
||||
s27=0x0000001b
|
||||
s28=0x0000001c
|
||||
s29=0x0000001d
|
||||
s30=0x0000001e
|
||||
s31=0x0000001f
|
||||
}
|
||||
}
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user