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[PowerPC][NFC] Simplify vector unpacked instr classes (#160564)

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https://github.com/llvm/llvm-project/pull/151004/files#r2240893226
This commit is contained in:
Lei Huang
2025-09-24 14:27:42 -04:00
committed by GitHub
parent 3c53adec68
commit 89eeecd15c
1 changed files with 15 additions and 35 deletions
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50
llvm/lib/Target/PowerPC/PPCInstrFuture.td
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@@ -45,79 +45,59 @@ multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
}
}
class VXForm_VRTB5<bits<11> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
class VXForm_VRTB5_Base<bits<11> xo, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<4, OOL, IOL, asmstr, NoItinerary> {
bits<5> VRT;
bits<5> VRB;
let Pattern = pattern;
let Inst{6...10} = VRT;
let Inst{11...15} = R;
let Inst{16...20} = VRB;
let Inst{21...31} = xo;
}
class VXForm_VRTB5<bits<11> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {
let Inst{11...15} = R;
}
class VXForm_VRTB5_UIM2<bits<11> xo, bits<3> R, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<4, OOL, IOL, asmstr, NoItinerary> {
bits<5> VRT;
bits<5> VRB;
: VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {
bits<2> UIM;
let Pattern = pattern;
let Inst{6...10} = VRT;
let Inst{11...13} = R;
let Inst{14...15} = UIM;
let Inst{16...20} = VRB;
let Inst{21...31} = xo;
}
class VXForm_VRTB5_UIM1<bits<11> xo, bits<4> R, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<4, OOL, IOL, asmstr, NoItinerary> {
bits<5> VRT;
bits<5> VRB;
: VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {
bits<1> UIM;
let Pattern = pattern;
let Inst{6...10} = VRT;
let Inst{11...14} = R;
let Inst{15} = UIM;
let Inst{16...20} = VRB;
let Inst{21...31} = xo;
}
class VXForm_VRTB5_UIM3<bits<11> xo, bits<2> R, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<4, OOL, IOL, asmstr, NoItinerary> {
bits<5> VRT;
bits<5> VRB;
: VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {
bits<3> UIM;
let Pattern = pattern;
let Inst{6...10} = VRT;
let Inst{11...12} = R;
let Inst{13...15} = UIM;
let Inst{16...20} = VRB;
let Inst{21...31} = xo;
}
class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
bits<5> VRT;
list<dag> pattern>
: VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {
bits<5> VRA;
bits<5> VRB;
let Pattern = pattern;
let Inst{6...10} = VRT;
let Inst{11...15} = VRA;
let Inst{16...20} = VRB;
let Inst{21...31} = xo;
}
class XX3Form_XTBp5_M2<bits<9> xo, dag OOL, dag IOL, string asmstr,