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[HWASan] Mention x86_64 aliasing mode in design doc.
Reviewed By: eugenis Differential Revision: https://reviews.llvm.org/D98892
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@@ -19,13 +19,17 @@ The redzones, the quarantine, and, to a less extent, the shadow, are the
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sources of AddressSanitizer's memory overhead.
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See the `AddressSanitizer paper`_ for details.
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AArch64 has the `Address Tagging`_ (or top-byte-ignore, TBI), a hardware feature that allows
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software to use 8 most significant bits of a 64-bit pointer as
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AArch64 has `Address Tagging`_ (or top-byte-ignore, TBI), a hardware feature that allows
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software to use the 8 most significant bits of a 64-bit pointer as
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a tag. HWASAN uses `Address Tagging`_
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to implement a memory safety tool, similar to :doc:`AddressSanitizer`,
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but with smaller memory overhead and slightly different (mostly better)
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accuracy guarantees.
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Intel's `Linear Address Masking`_ (LAM) also provides address tagging for
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x86_64, though it is not widely available in hardware yet. For x86_64, HWASAN
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has a limited implementation using page aliasing instead.
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Algorithm
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=========
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* Every heap/stack/global memory object is forcibly aligned by `TG` bytes
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@@ -266,7 +270,15 @@ before every load and store by compiler instrumentation, but this variant
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will have limited deployability since not all of the code is
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typically instrumented.
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The HWASAN's approach is not applicable to 32-bit architectures.
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On x86_64, HWASAN utilizes page aliasing to place tags in userspace address
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bits. Currently only heap tagging is supported. The page aliases rely on
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shared memory, which will cause heap memory to be shared between processes if
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the application calls ``fork()``. Therefore x86_64 is really only safe for
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applications that do not fork.
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HWASAN does not currently support 32-bit architectures since they do not
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support `Address Tagging`_ and the address space is too constrained to easily
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implement page aliasing.
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Related Work
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@@ -284,4 +296,4 @@ Related Work
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.. _SPARC ADI: https://lazytyped.blogspot.com/2017/09/getting-started-with-adi.html
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.. _AddressSanitizer paper: https://www.usenix.org/system/files/conference/atc12/atc12-final39.pdf
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.. _Address Tagging: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/ch12s05s01.html
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.. _Linear Address Masking: https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
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