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[RISCV] Make (sext_inreg X, i1) legal for XTHeadBb to cover the existing isel pattern.

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I just happened to notice the untested isel pattern.
This commit is contained in:
Craig Topper
2024-10-11 15:54:46 -07:00
parent 637054640e
commit 902520256b
3 changed files with 95 additions and 1 deletions
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3
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@@ -299,7 +299,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction({ISD::VAARG, ISD::VACOPY, ISD::VAEND}, MVT::Other, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
if (!Subtarget.hasVendorXTHeadBb())
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);

31
llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
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@@ -266,6 +266,37 @@ define i64 @cttz_i64(i64 %a) nounwind {
ret i64 %1
}
define i32 @sexti1_i32(i32 %a) nounwind {
; RV32I-LABEL: sexti1_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 31
; RV32I-NEXT: srai a0, a0, 31
; RV32I-NEXT: ret
;
; RV32XTHEADBB-LABEL: sexti1_i32:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: th.ext a0, a0, 0, 0
; RV32XTHEADBB-NEXT: ret
%shl = shl i32 %a, 31
%shr = ashr exact i32 %shl, 31
ret i32 %shr
}
define i32 @sexti1_i32_2(i1 %a) nounwind {
; RV32I-LABEL: sexti1_i32_2:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 31
; RV32I-NEXT: srai a0, a0, 31
; RV32I-NEXT: ret
;
; RV32XTHEADBB-LABEL: sexti1_i32_2:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: th.ext a0, a0, 0, 0
; RV32XTHEADBB-NEXT: ret
%sext = sext i1 %a to i32
ret i32 %sext
}
define i32 @sextb_i32(i32 %a) nounwind {
; RV32I-LABEL: sextb_i32:
; RV32I: # %bb.0:

62
llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
View File

@@ -558,6 +558,68 @@ define i64 @cttz_i64(i64 %a) nounwind {
ret i64 %1
}
define signext i32 @sexti1_i32(i32 signext %a) nounwind {
; RV64I-LABEL: sexti1_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: srai a0, a0, 63
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: sexti1_i32:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
; RV64XTHEADBB-NEXT: ret
%shl = shl i32 %a, 31
%shr = ashr exact i32 %shl, 31
ret i32 %shr
}
define signext i32 @sexti1_i32_2(i1 %a) nounwind {
; RV64I-LABEL: sexti1_i32_2:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: srai a0, a0, 63
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: sexti1_i32_2:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
; RV64XTHEADBB-NEXT: ret
%sext = sext i1 %a to i32
ret i32 %sext
}
define i64 @sexti1_i64(i64 %a) nounwind {
; RV64I-LABEL: sexti1_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: srai a0, a0, 63
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: sexti1_i64:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
; RV64XTHEADBB-NEXT: ret
%shl = shl i64 %a, 63
%shr = ashr exact i64 %shl, 63
ret i64 %shr
}
define i64 @sexti1_i64_2(i1 %a) nounwind {
; RV64I-LABEL: sexti1_i64_2:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: srai a0, a0, 63
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: sexti1_i64_2:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
; RV64XTHEADBB-NEXT: ret
%sext = sext i1 %a to i64
ret i64 %sext
}
define signext i32 @sextb_i32(i32 signext %a) nounwind {
; RV64I-LABEL: sextb_i32:
; RV64I: # %bb.0: