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[X86][Haswell][SchedModel] Add architecture specific scheduling models.

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Group: Integer MMX and XMM instructions.
Sub-group: Logic instructions.

<rdar://problem/15607571>

llvm-svn: 215916
This commit is contained in:
Quentin Colombet
2014-08-18 17:55:41 +00:00
parent e9f8b4b7ac
commit 91513d9522
1 changed files with 31 additions and 0 deletions
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31
llvm/lib/Target/X86/X86SchedHaswell.td
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@@ -1505,4 +1505,35 @@ def WritePMULLDm : SchedWriteRes<[HWPort0, HWPort23]> {
}
def : InstRW<[WritePMULLDm, ReadAfterLd], (instregex "(V?)PMULLD(Y?)rm")>;
//-- Logic instructions --//
// PTEST.
// v,v.
def WritePTESTr : SchedWriteRes<[HWPort0, HWPort5]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1, 1];
}
def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rr")>;
// v,m.
def WritePTESTm : SchedWriteRes<[HWPort0, HWPort5, HWPort23]> {
let Latency = 6;
let NumMicroOps = 3;
let ResourceCycles = [1, 1, 1];
}
def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rm")>;
// PSLL,PSRL,PSRA W/D/Q.
// x,x / v,v,x.
def WritePShift : SchedWriteRes<[HWPort0, HWPort5]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1, 1];
}
def : InstRW<[WritePShift], (instregex "(V?)PS(LL|RL|RA)(W|D|Q)(Y?)rr")>;
// PSLL,PSRL DQ.
def : InstRW<[WriteP5], (instregex "(V?)PS(R|L)LDQ(Y?)ri")>;
} // SchedModel