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[RISCV][MC] Split tests for A into Zaamo and Zalrsc parts

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So that we don't duplicate tests in later patch.

Reviewers: topperc, dtcxzyw, asb

Reviewed By: asb

Pull Request: https://github.com/llvm/llvm-project/pull/79111
This commit is contained in:
Wang Pengcheng
2024-01-24 10:49:14 +08:00
committed by GitHub
parent 63f742c15f
commit 93248729cf
8 changed files with 92 additions and 71 deletions
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7
llvm/test/MC/RISCV/rv32a-invalid.s → llvm/test/MC/RISCV/rv32zaamo-invalid.s
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@@ -4,15 +4,8 @@
amoswap.w a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
amomin.w a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
amomin.w a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
# Only .aq, .rl, and .aqrl suffixes are valid
amoxor.w.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.w.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.w. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
# lr only takes two operands
lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
# Note: errors for use of RV64A instructions for RV32 are checked in
# rv64a-valid.s

26
llvm/test/MC/RISCV/rv32a-valid.s → llvm/test/MC/RISCV/rv32zaamo-valid.s
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@@ -9,32 +9,6 @@
# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
lr.w t0, (t1)
# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
lr.w.aq t1, (t2)
# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
lr.w.rl t2, (t3)
# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
lr.w.aqrl t3, (t4)
# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
sc.w t6, t5, (t4)
# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
sc.w.aq t5, t4, (t3)
# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
sc.w.rl t4, t3, (t2)
# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
sc.w.aqrl t3, t2, (t1)
# CHECK-ASM-AND-OBJ: amoswap.w a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x08]
amoswap.w a4, ra, (s0)

7
llvm/test/MC/RISCV/rv32zalrsc-invalid.s Normal file
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@@ -0,0 +1,7 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 | FileCheck %s
# Final operand must have parentheses
lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
# lr only takes two operands
lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction

36
llvm/test/MC/RISCV/rv32zalrsc-valid.s Normal file
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@@ -0,0 +1,36 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+a -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a < %s \
# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
lr.w t0, (t1)
# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
lr.w.aq t1, (t2)
# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
lr.w.rl t2, (t3)
# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
lr.w.aqrl t3, (t4)
# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
sc.w t6, t5, (t4)
# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
sc.w.aq t5, t4, (t3)
# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
sc.w.rl t4, t3, (t2)
# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
sc.w.aqrl t3, t2, (t1)

4
llvm/test/MC/RISCV/rv64a-invalid.s → llvm/test/MC/RISCV/rv64zaamo-invalid.s
View File

@@ -4,12 +4,8 @@
amoswap.d a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
amomin.d a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
amomin.d a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
# Only .aq, .rl, and .aqrl suffixes are valid
amoxor.d.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.d.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.d. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
# lr only takes two operands
lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction

34
llvm/test/MC/RISCV/rv64a-valid.s → llvm/test/MC/RISCV/rv64zaamo-valid.s
View File

@@ -7,40 +7,6 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
lr.d t0, (t1)
# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
lr.d.aq t1, (t2)
# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
lr.d.rl t2, (t3)
# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
lr.d.aqrl t3, (t4)
# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
sc.d t6, t5, (t4)
# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
sc.d.aq t5, t4, (t3)
# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
sc.d.rl t4, t3, (t2)
# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
sc.d.aqrl t3, t2, (t1)
# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}

7
llvm/test/MC/RISCV/rv64zalrsc-invalid.s Normal file
View File

@@ -0,0 +1,7 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+a < %s 2>&1 | FileCheck %s
# Final operand must have parentheses
lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
# lr only takes two operands
lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction

42
llvm/test/MC/RISCV/rv64zalrsc-valid.s Normal file
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@@ -0,0 +1,42 @@
# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
lr.d t0, (t1)
# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
lr.d.aq t1, (t2)
# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
lr.d.rl t2, (t3)
# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
lr.d.aqrl t3, (t4)
# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
sc.d t6, t5, (t4)
# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
sc.d.aq t5, t4, (t3)
# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
sc.d.rl t4, t3, (t2)
# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
sc.d.aqrl t3, t2, (t1)