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[RISCV] Rematerialize vmv.s.x and vfmv.s.f (#108012)
Continuing with #107993 and #108007, this handles the last of the main rematerializable vector instructions. There's an extra spill in one of the test cases, but it's likely noise from the spill weights and isn't an issue in practice.
This commit is contained in:
Luke Lau
GitHub
@@ -172,6 +172,8 @@ bool RISCVInstrInfo::isReallyTriviallyReMaterializable(
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case RISCV::VMV_V_X:
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case RISCV::VFMV_V_F:
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case RISCV::VMV_V_I:
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case RISCV::VMV_S_X:
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case RISCV::VFMV_S_F:
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case RISCV::VID_V:
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if (MI.getOperand(1).isUndef() &&
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/* After RISCVInsertVSETVLI most pseudos will have implicit uses on vl
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@@ -6764,7 +6764,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
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Pseudo<(outs GPR:$rd), (ins VR:$rs2, ixlenimm:$sew), []>,
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Sched<[WriteVMovXS, ReadVMovXS]>,
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RISCVVPseudo;
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let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
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let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, isReMaterializable = 1,
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Constraints = "$rd = $rs1" in
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def PseudoVMV_S_X: Pseudo<(outs VR:$rd),
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(ins VR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),
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@@ -6787,7 +6787,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
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(ins VR:$rs2, ixlenimm:$sew), []>,
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Sched<[WriteVMovFS, ReadVMovFS]>,
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RISCVVPseudo;
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let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F,
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let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1,
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Constraints = "$rd = $rs1" in
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def "PseudoVFMV_S_" # f.FX :
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Pseudo<(outs VR:$rd),
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File diff suppressed because it is too large
Load Diff
@@ -377,3 +377,133 @@ define void @vfmv.v.f(ptr %p, double %x) {
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store volatile double %x, ptr %p
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ret void
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}
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define void @vmv.s.x(ptr %p, i64 %x) {
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; POSTRA-LABEL: vmv.s.x:
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; POSTRA: # %bb.0:
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; POSTRA-NEXT: vsetvli a2, zero, e64, m1, ta, ma
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; POSTRA-NEXT: vmv.s.x v8, a1
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: vl8re64.v v16, (a0)
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; POSTRA-NEXT: vl8re64.v v24, (a0)
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; POSTRA-NEXT: vl8re64.v v0, (a0)
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; POSTRA-NEXT: vl8re64.v v8, (a0)
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: vs8r.v v0, (a0)
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; POSTRA-NEXT: vs8r.v v24, (a0)
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; POSTRA-NEXT: vs8r.v v16, (a0)
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; POSTRA-NEXT: vmv.s.x v8, a1
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: sd a1, 0(a0)
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; POSTRA-NEXT: ret
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;
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; PRERA-LABEL: vmv.s.x:
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; PRERA: # %bb.0:
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; PRERA-NEXT: addi sp, sp, -16
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; PRERA-NEXT: .cfi_def_cfa_offset 16
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; PRERA-NEXT: csrr a2, vlenb
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; PRERA-NEXT: slli a2, a2, 3
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; PRERA-NEXT: sub sp, sp, a2
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; PRERA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; PRERA-NEXT: vsetvli a2, zero, e64, m1, ta, ma
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; PRERA-NEXT: vmv.s.x v8, a1
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; PRERA-NEXT: vs8r.v v8, (a0)
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; PRERA-NEXT: vl8re64.v v16, (a0)
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; PRERA-NEXT: addi a2, sp, 16
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; PRERA-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
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; PRERA-NEXT: vl8re64.v v24, (a0)
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; PRERA-NEXT: vl8re64.v v0, (a0)
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; PRERA-NEXT: vl8re64.v v16, (a0)
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; PRERA-NEXT: vs8r.v v16, (a0)
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; PRERA-NEXT: vs8r.v v0, (a0)
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; PRERA-NEXT: vs8r.v v24, (a0)
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; PRERA-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload
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; PRERA-NEXT: vs8r.v v16, (a0)
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; PRERA-NEXT: vs8r.v v8, (a0)
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; PRERA-NEXT: sd a1, 0(a0)
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; PRERA-NEXT: csrr a0, vlenb
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; PRERA-NEXT: slli a0, a0, 3
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; PRERA-NEXT: add sp, sp, a0
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; PRERA-NEXT: addi sp, sp, 16
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; PRERA-NEXT: ret
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%vmv.s.x = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64> poison, i64 %x, i64 -1)
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store volatile <vscale x 8 x i64> %vmv.s.x, ptr %p
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%a = load volatile <vscale x 8 x i64>, ptr %p
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%b = load volatile <vscale x 8 x i64>, ptr %p
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%c = load volatile <vscale x 8 x i64>, ptr %p
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%d = load volatile <vscale x 8 x i64>, ptr %p
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store volatile <vscale x 8 x i64> %d, ptr %p
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store volatile <vscale x 8 x i64> %c, ptr %p
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store volatile <vscale x 8 x i64> %b, ptr %p
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store volatile <vscale x 8 x i64> %a, ptr %p
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store volatile <vscale x 8 x i64> %vmv.s.x, ptr %p
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store volatile i64 %x, ptr %p
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ret void
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}
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define void @vfmv.s.f(ptr %p, double %x) {
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; POSTRA-LABEL: vfmv.s.f:
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; POSTRA: # %bb.0:
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; POSTRA-NEXT: vsetvli a1, zero, e64, m1, ta, ma
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; POSTRA-NEXT: vfmv.s.f v8, fa0
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: vl8re64.v v16, (a0)
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; POSTRA-NEXT: vl8re64.v v24, (a0)
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; POSTRA-NEXT: vl8re64.v v0, (a0)
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; POSTRA-NEXT: vl8re64.v v8, (a0)
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: vs8r.v v0, (a0)
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; POSTRA-NEXT: vs8r.v v24, (a0)
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; POSTRA-NEXT: vs8r.v v16, (a0)
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; POSTRA-NEXT: vfmv.s.f v8, fa0
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: fsd fa0, 0(a0)
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; POSTRA-NEXT: ret
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;
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; PRERA-LABEL: vfmv.s.f:
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; PRERA: # %bb.0:
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; PRERA-NEXT: addi sp, sp, -16
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; PRERA-NEXT: .cfi_def_cfa_offset 16
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; PRERA-NEXT: csrr a1, vlenb
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; PRERA-NEXT: slli a1, a1, 3
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; PRERA-NEXT: sub sp, sp, a1
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; PRERA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; PRERA-NEXT: vsetvli a1, zero, e64, m1, ta, ma
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; PRERA-NEXT: vfmv.s.f v8, fa0
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; PRERA-NEXT: vs8r.v v8, (a0)
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; PRERA-NEXT: vl8re64.v v16, (a0)
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; PRERA-NEXT: addi a1, sp, 16
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; PRERA-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
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; PRERA-NEXT: vl8re64.v v24, (a0)
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; PRERA-NEXT: vl8re64.v v0, (a0)
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; PRERA-NEXT: vl8re64.v v16, (a0)
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; PRERA-NEXT: vs8r.v v16, (a0)
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; PRERA-NEXT: vs8r.v v0, (a0)
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; PRERA-NEXT: vs8r.v v24, (a0)
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; PRERA-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
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; PRERA-NEXT: vs8r.v v16, (a0)
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; PRERA-NEXT: vs8r.v v8, (a0)
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; PRERA-NEXT: fsd fa0, 0(a0)
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; PRERA-NEXT: csrr a0, vlenb
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; PRERA-NEXT: slli a0, a0, 3
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; PRERA-NEXT: add sp, sp, a0
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; PRERA-NEXT: addi sp, sp, 16
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; PRERA-NEXT: ret
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%vfmv.s.f = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> poison, double %x, i64 -1)
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store volatile <vscale x 8 x double> %vfmv.s.f, ptr %p
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%a = load volatile <vscale x 8 x double>, ptr %p
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%b = load volatile <vscale x 8 x double>, ptr %p
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%c = load volatile <vscale x 8 x double>, ptr %p
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%d = load volatile <vscale x 8 x double>, ptr %p
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store volatile <vscale x 8 x double> %d, ptr %p
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store volatile <vscale x 8 x double> %c, ptr %p
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store volatile <vscale x 8 x double> %b, ptr %p
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store volatile <vscale x 8 x double> %a, ptr %p
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store volatile <vscale x 8 x double> %vfmv.s.f, ptr %p
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store volatile double %x, ptr %p
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ret void
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}
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