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[X86] Add test coverage for the concatenation of vXf64 sqrt intrinsics (#170158)

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Simon Pilgrim
2025-12-01 16:20:43 +00:00
committed by GitHub
parent 46c34bec13
commit 9f54c2a674
1 changed files with 84 additions and 0 deletions
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84
llvm/test/CodeGen/X86/combine-fsqrt.ll
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@@ -5,6 +5,25 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX1OR2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512
define <4 x double> @concat_sqrt_v4f64_v2f64(<2 x double> %a0, <2 x double> %a1) {
; SSE-LABEL: concat_sqrt_v4f64_v2f64:
; SSE: # %bb.0:
; SSE-NEXT: sqrtpd %xmm0, %xmm0
; SSE-NEXT: sqrtpd %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: concat_sqrt_v4f64_v2f64:
; AVX: # %bb.0:
; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vsqrtpd %ymm0, %ymm0
; AVX-NEXT: retq
%v0 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a0)
%v1 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a1)
%res = shufflevector <2 x double> %v0, <2 x double> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %res
}
define <8 x float> @concat_sqrt_v8f32_v4f32(<4 x float> %a0, <4 x float> %a1) {
; SSE-LABEL: concat_sqrt_v8f32_v4f32:
; SSE: # %bb.0:
@@ -24,6 +43,44 @@ define <8 x float> @concat_sqrt_v8f32_v4f32(<4 x float> %a0, <4 x float> %a1) {
ret <8 x float> %res
}
define <8 x double> @concat_sqrt_v8f64_v2f64(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3) {
; SSE-LABEL: concat_sqrt_v8f64_v2f64:
; SSE: # %bb.0:
; SSE-NEXT: sqrtpd %xmm0, %xmm0
; SSE-NEXT: sqrtpd %xmm1, %xmm1
; SSE-NEXT: sqrtpd %xmm2, %xmm2
; SSE-NEXT: sqrtpd %xmm3, %xmm3
; SSE-NEXT: retq
;
; AVX1OR2-LABEL: concat_sqrt_v8f64_v2f64:
; AVX1OR2: # %bb.0:
; AVX1OR2-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm2
; AVX1OR2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1OR2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1OR2-NEXT: vsqrtpd %ymm0, %ymm0
; AVX1OR2-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm1
; AVX1OR2-NEXT: vsqrtpd %ymm1, %ymm1
; AVX1OR2-NEXT: retq
;
; AVX512-LABEL: concat_sqrt_v8f64_v2f64:
; AVX512: # %bb.0:
; AVX512-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm2
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512-NEXT: vsqrtpd %zmm0, %zmm0
; AVX512-NEXT: retq
%v0 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a0)
%v1 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a1)
%v2 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a2)
%v3 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a3)
%r01 = shufflevector <2 x double> %v0, <2 x double> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%r23 = shufflevector <2 x double> %v2, <2 x double> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = shufflevector <4 x double> %r01, <4 x double> %r23, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x double> %res
}
define <16 x float> @concat_sqrt_v16f32_v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3) {
; SSE-LABEL: concat_sqrt_v16f32_v4f32:
; SSE: # %bb.0:
@@ -62,6 +119,33 @@ define <16 x float> @concat_sqrt_v16f32_v4f32(<4 x float> %a0, <4 x float> %a1,
ret <16 x float> %res
}
define <8 x double> @concat_sqrt_v8f64_v4f64(<4 x double> %a0, <4 x double> %a1) {
; SSE-LABEL: concat_sqrt_v8f64_v4f64:
; SSE: # %bb.0:
; SSE-NEXT: sqrtpd %xmm0, %xmm0
; SSE-NEXT: sqrtpd %xmm1, %xmm1
; SSE-NEXT: sqrtpd %xmm2, %xmm2
; SSE-NEXT: sqrtpd %xmm3, %xmm3
; SSE-NEXT: retq
;
; AVX1OR2-LABEL: concat_sqrt_v8f64_v4f64:
; AVX1OR2: # %bb.0:
; AVX1OR2-NEXT: vsqrtpd %ymm0, %ymm0
; AVX1OR2-NEXT: vsqrtpd %ymm1, %ymm1
; AVX1OR2-NEXT: retq
;
; AVX512-LABEL: concat_sqrt_v8f64_v4f64:
; AVX512: # %bb.0:
; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512-NEXT: vsqrtpd %zmm0, %zmm0
; AVX512-NEXT: retq
%v0 = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a0)
%v1 = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a1)
%res = shufflevector <4 x double> %v0, <4 x double> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x double> %res
}
define <16 x float> @concat_sqrt_v16f32_v8f32(<8 x float> %a0, <8 x float> %a1) {
; SSE-LABEL: concat_sqrt_v16f32_v8f32:
; SSE: # %bb.0: