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[ROCDL] Added asynccnt and tensorcnt wait ops (gfx1250) (#163533)

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This patch introduces some missing `s.wait.asynccnt` and `tensorcnt`
instructions in the ROCDL dialect.

The op is lowered to `@llvm.amdgcn.s.wait.asynccnt(i16 0)` and
`@llvm.amdgcn.s.wait.tensorcnt(i16 0)` intrinsic calls
This commit is contained in:
ravil-mobile
2025-10-15 21:13:53 +02:00
committed by GitHub
parent b516dcc998
commit a561a0802d
3 changed files with 54 additions and 0 deletions
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26
mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
View File

@@ -412,6 +412,32 @@ def ROCDL_WaitExpcntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.expcnt", [], 0, [0],
let assemblyFormat = "$count attr-dict";
}
def ROCDL_WaitAsynccntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.asynccnt", [], 0, [0], ["count"]>,
Arguments<(ins I16Attr:$count)> {
let summary = "Wait until ASYNCCNT is less than or equal to `count`";
let description = [{
Wait for the counter specified to be less-than or equal-to the `count`
before continuing.
Available on gfx1250+.
}];
let results = (outs);
let assemblyFormat = "$count attr-dict";
}
def ROCDL_WaitTensorcntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.tensorcnt", [], 0, [0], ["count"]>,
Arguments<(ins I16Attr:$count)> {
let summary = "Wait until TENSORCNT is less than or equal to `count`";
let description = [{
Wait for the counter specified to be less-than or equal-to the `count`
before continuing.
Available on gfx1250+.
}];
let results = (outs);
let assemblyFormat = "$count attr-dict";
}
def ROCDL_SetPrioOp : ROCDL_ConcreteNonMemIntrOp<"s.setprio", [], 0, [0], ["priority"]>,
Arguments<(ins I16Attr:$priority)> {
let assemblyFormat = "$priority attr-dict";

14
mlir/test/Dialect/LLVMIR/rocdl.mlir
View File

@@ -1035,6 +1035,20 @@ llvm.func @rocdl.s.wait.expcnt() {
llvm.return
}
llvm.func @rocdl.s.wait.asynccnt() {
// CHECK-LABEL: rocdl.s.wait.asynccnt
// CHECK: rocdl.s.wait.asynccnt 0
rocdl.s.wait.asynccnt 0
llvm.return
}
llvm.func @rocdl.s.wait.tensorcnt() {
// CHECK-LABEL: rocdl.s.wait.tensorcnt
// CHECK: rocdl.s.wait.tensorcnt 0
rocdl.s.wait.tensorcnt 0
llvm.return
}
// -----
llvm.func @rocdl.readfirstlane(%src : f32) -> f32 {

14
mlir/test/Target/LLVMIR/rocdl.mlir
View File

@@ -276,6 +276,20 @@ llvm.func @rocdl.s.wait.expcnt() {
llvm.return
}
llvm.func @rocdl.s.wait.asynccnt() {
// CHECK-LABEL: rocdl.s.wait.asynccnt
// CHECK-NEXT: call void @llvm.amdgcn.s.wait.asynccnt(i16 0)
rocdl.s.wait.asynccnt 0
llvm.return
}
llvm.func @rocdl.s.wait.tensorcnt() {
// CHECK-LABEL: rocdl.s.wait.tensorcnt
// CHECK-NEXT: call void @llvm.amdgcn.s.wait.tensorcnt(i16 0)
rocdl.s.wait.tensorcnt 0
llvm.return
}
llvm.func @rocdl.setprio() {
// CHECK: call void @llvm.amdgcn.s.setprio(i16 0)
rocdl.s.setprio 0