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[RISCV] Add FallbackRegAltNameIndex to ABIRegAltName.

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Remove now redundant fake ABI names from vector registers.

This also fixes a crash that occurs if you use fflags as an instruction
operand in the assembly and use -debug. It's not a valid register
for any instruction since this wouldn't be common. It doesn't have
an ABI name so it crashes the register printing in the debug output.
This commit is contained in:
Craig Topper
2023-03-22 10:07:18 -07:00
parent 164b046ebf
commit a67e989cd2
1 changed files with 39 additions and 43 deletions
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82
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
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@@ -45,6 +45,7 @@ class RISCVReg64<RISCVReg32 subreg>
let SubRegIndices = [sub_32];
}
let FallbackRegAltNameIndex = NoRegAltName in
def ABIRegAltName : RegAltNameIndex;
def sub_vrm4_0 : SubRegIndex<256>;
@@ -415,51 +416,46 @@ class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> {
}
// Vector registers
let RegAltNameIndices = [ABIRegAltName] in {
foreach Index = 0-31 in {
def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 96)]>;
}
foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
24, 26, 28, 30] in {
def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index,
[!cast<Register>("V"#Index),
!cast<Register>("V"#!add(Index, 1))],
["v"#Index]>,
DwarfRegAlias<!cast<Register>("V"#Index)> {
let SubRegIndices = [sub_vrm1_0, sub_vrm1_1];
}
}
foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in {
def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index,
[!cast<Register>("V"#Index#"M2"),
!cast<Register>("V"#!add(Index, 2)#"M2")],
["v"#Index]>,
DwarfRegAlias<!cast<Register>("V"#Index)> {
let SubRegIndices = [sub_vrm2_0, sub_vrm2_1];
}
}
foreach Index = [0, 8, 16, 24] in {
def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index,
[!cast<Register>("V"#Index#"M4"),
!cast<Register>("V"#!add(Index, 4)#"M4")],
["v"#Index]>,
DwarfRegAlias<!cast<Register>("V"#Index)> {
let SubRegIndices = [sub_vrm4_0, sub_vrm4_1];
}
}
def VTYPE : RISCVReg<0, "vtype", ["vtype"]>;
def VL : RISCVReg<0, "vl", ["vl"]>;
def VXSAT : RISCVReg<0, "vxsat", ["vxsat"]>;
def VXRM : RISCVReg<0, "vxrm", ["vxrm"]>;
let isConstant = true in
def VLENB : RISCVReg<0, "vlenb", ["vlenb"]>,
DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>;
foreach Index = 0-31 in {
def V#Index : RISCVReg<Index, "v"#Index>, DwarfRegNum<[!add(Index, 96)]>;
}
foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
24, 26, 28, 30] in {
def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index,
[!cast<Register>("V"#Index),
!cast<Register>("V"#!add(Index, 1))]>,
DwarfRegAlias<!cast<Register>("V"#Index)> {
let SubRegIndices = [sub_vrm1_0, sub_vrm1_1];
}
}
foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in {
def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index,
[!cast<Register>("V"#Index#"M2"),
!cast<Register>("V"#!add(Index, 2)#"M2")]>,
DwarfRegAlias<!cast<Register>("V"#Index)> {
let SubRegIndices = [sub_vrm2_0, sub_vrm2_1];
}
}
foreach Index = [0, 8, 16, 24] in {
def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index,
[!cast<Register>("V"#Index#"M4"),
!cast<Register>("V"#!add(Index, 4)#"M4")]>,
DwarfRegAlias<!cast<Register>("V"#Index)> {
let SubRegIndices = [sub_vrm4_0, sub_vrm4_1];
}
}
def VTYPE : RISCVReg<0, "vtype">;
def VL : RISCVReg<0, "vl">;
def VXSAT : RISCVReg<0, "vxsat">;
def VXRM : RISCVReg<0, "vxrm">;
let isConstant = true in
def VLENB : RISCVReg<0, "vlenb">,
DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>;
def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
(add VTYPE, VL, VLENB)> {
let RegInfos = XLenRI;