intel/llvm
1
0
Fork 0
mirror of https://github.com/intel/llvm.git synced 2026-01-26 12:26:52 +08:00
Code Issues Packages Projects Releases Wiki Activity

Remove Config->Rela and define Config->isRela() instead.

Browse Source 
llvm-svn: 297108
This commit is contained in:
Rui Ueyama
2017-03-07 00:43:53 +00:00
parent df8eb17d21
commit af6198d96d
5 changed files with 33 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
lld/ELF/Config.h
View File

@@ -162,6 +162,26 @@ struct Configuration {
unsigned Optimize;
unsigned ThinLTOJobs;
// The ELF spec defines two types of relocation table entries, RELA and
// REL. RELA is a triplet of (offset, info, addend) while REL is a
// tuple of (offset, info). Addends for REL are implicit and read from
// the location where the relocations are applied. So, REL is more
// compact than RELA but requires a bit of more work to process.
//
// (From the linker writer's view, this distinction is not necessary.
// If the ELF had chosen whichever and sticked with it, it would have
// been easier to write code to process relocations, but it's too late
// to change the spec.)
//
// Each ABI defines its relocation type. This function returns that.
// As far as we know, all 64-bit ABIs are using RELA. A few 32-bit ABIs
// are using RELA too.
bool isRela() const {
bool is64 = (EKind == ELF64LEKind || EKind == ELF64BEKind);
bool isX32Abi = (EKind == ELF32LEKind && EMachine == llvm::ELF::EM_X86_64);
return is64 || isX32Abi || MipsN32Abi;
}
// Returns true if we need to pass through relocations in input
// files to the output file. Usually false because we consume
// relocations.

2
lld/ELF/Driver.cpp
View File

@@ -803,8 +803,6 @@ template <class ELFT> void LinkerDriver::link(opt::InputArgList &Args) {
Target = createTarget();
ScriptBase = Script<ELFT>::X = make<LinkerScript<ELFT>>();
Config->Rela =
ELFT::Is64Bits || Config->EMachine == EM_X86_64 || Config->MipsN32Abi;
Config->MaxPageSize = getMaxPageSize(Args);
Config->ImageBase = getImageBase(Args);

4
lld/ELF/InputSection.cpp
View File

@@ -228,7 +228,7 @@ void InputSection::copyRelocations(uint8_t *Buf, ArrayRef<RelTy> Rels) {
auto *P = reinterpret_cast<typename ELFT::Rela *>(Buf);
Buf += sizeof(RelTy);
if (Config->Rela)
if (Config->isRela())
P->r_addend = getAddend<ELFT>(Rel);
// Output section VA is zero for -r, so r_offset is an offset within the
@@ -254,7 +254,7 @@ void InputSection::copyRelocations(uint8_t *Buf, ArrayRef<RelTy> Rels) {
continue;
}
if (Config->Rela) {
if (Config->isRela()) {
P->r_addend += Body.getVA<ELFT>() - Section->OutSec->Addr;
} else if (Config->Relocatable) {
const uint8_t *BufLoc = RelocatedSection->Data.begin() + Rel.r_offset;

14
lld/ELF/SyntheticSections.cpp
View File

@@ -1087,7 +1087,7 @@ template <class ELFT> void DynamicSection<ELFT>::finalizeContents() {
this->Link = In<ELFT>::DynStrTab->OutSec->SectionIndex;
if (In<ELFT>::RelaDyn->OutSec->Size > 0) {
bool IsRela = Config->Rela;
bool IsRela = Config->isRela();
add({IsRela ? DT_RELA : DT_REL, In<ELFT>::RelaDyn});
add({IsRela ? DT_RELASZ : DT_RELSZ, In<ELFT>::RelaDyn->OutSec->Size});
add({IsRela ? DT_RELAENT : DT_RELENT,
@@ -1107,7 +1107,7 @@ template <class ELFT> void DynamicSection<ELFT>::finalizeContents() {
add({DT_PLTRELSZ, In<ELFT>::RelaPlt->OutSec->Size});
add({Config->EMachine == EM_MIPS ? DT_MIPS_PLTGOT : DT_PLTGOT,
In<ELFT>::GotPlt});
add({DT_PLTREL, uint64_t(Config->Rela ? DT_RELA : DT_REL)});
add({DT_PLTREL, uint64_t(Config->isRela() ? DT_RELA : DT_REL)});
}
add({DT_SYMTAB, In<ELFT>::DynSymTab});
@@ -1215,10 +1215,10 @@ template <class ELFT> uint32_t DynamicReloc<ELFT>::getSymIndex() const {
template <class ELFT>
RelocationSection<ELFT>::RelocationSection(StringRef Name, bool Sort)
: SyntheticSection(SHF_ALLOC, Config->Rela ? SHT_RELA : SHT_REL,
: SyntheticSection(SHF_ALLOC, Config->isRela() ? SHT_RELA : SHT_REL,
sizeof(uintX_t), Name),
Sort(Sort) {
this->Entsize = Config->Rela ? sizeof(Elf_Rela) : sizeof(Elf_Rel);
this->Entsize = Config->isRela() ? sizeof(Elf_Rela) : sizeof(Elf_Rel);
}
template <class ELFT>
@@ -1242,9 +1242,9 @@ template <class ELFT> void RelocationSection<ELFT>::writeTo(uint8_t *Buf) {
uint8_t *BufBegin = Buf;
for (const DynamicReloc<ELFT> &Rel : Relocs) {
auto *P = reinterpret_cast<Elf_Rela *>(Buf);
Buf += Config->Rela ? sizeof(Elf_Rela) : sizeof(Elf_Rel);
Buf += Config->isRela() ? sizeof(Elf_Rela) : sizeof(Elf_Rel);
if (Config->Rela)
if (Config->isRela())
P->r_addend = Rel.getAddend();
P->r_offset = Rel.getOffset();
if (Config->EMachine == EM_MIPS && Rel.getInputSec() == In<ELFT>::MipsGot)
@@ -1256,7 +1256,7 @@ template <class ELFT> void RelocationSection<ELFT>::writeTo(uint8_t *Buf) {
}
if (Sort) {
if (Config->Rela)
if (Config->isRela())
std::stable_sort((Elf_Rela *)BufBegin,
(Elf_Rela *)BufBegin + Relocs.size(),
compRelocations<ELFT, Elf_Rela>);

8
lld/ELF/Writer.cpp
View File

@@ -312,7 +312,7 @@ template <class ELFT> void Writer<ELFT>::createSyntheticSections() {
In<ELFT>::DynStrTab = make<StringTableSection<ELFT>>(".dynstr", true);
In<ELFT>::Dynamic = make<DynamicSection<ELFT>>();
In<ELFT>::RelaDyn = make<RelocationSection<ELFT>>(
Config->Rela ? ".rela.dyn" : ".rel.dyn", Config->ZCombreloc);
Config->isRela() ? ".rela.dyn" : ".rel.dyn", Config->ZCombreloc);
In<ELFT>::ShStrTab = make<StringTableSection<ELFT>>(".shstrtab", false);
Out::ElfHeader = make<OutputSection>("", 0, SHF_ALLOC);
@@ -421,7 +421,7 @@ template <class ELFT> void Writer<ELFT>::createSyntheticSections() {
// We always need to add rel[a].plt to output if it has entries.
// Even for static linking it can contain R_[*]_IRELATIVE relocations.
In<ELFT>::RelaPlt = make<RelocationSection<ELFT>>(
Config->Rela ? ".rela.plt" : ".rel.plt", false /*Sort*/);
Config->isRela() ? ".rela.plt" : ".rel.plt", false /*Sort*/);
Add(In<ELFT>::RelaPlt);
// The RelaIplt immediately follows .rel.plt (.rel.dyn for ARM) to ensure
@@ -774,10 +774,10 @@ static Symbol *addOptionalRegular(StringRef Name, InputSectionBase *IS,
template <class ELFT> void Writer<ELFT>::addRelIpltSymbols() {
if (In<ELFT>::DynSymTab)
return;
StringRef S = Config->Rela ? "__rela_iplt_start" : "__rel_iplt_start";
StringRef S = Config->isRela() ? "__rela_iplt_start" : "__rel_iplt_start";
addOptionalRegular<ELFT>(S, In<ELFT>::RelaIplt, 0);
S = Config->Rela ? "__rela_iplt_end" : "__rel_iplt_end";
S = Config->isRela() ? "__rela_iplt_end" : "__rel_iplt_end";
addOptionalRegular<ELFT>(S, In<ELFT>::RelaIplt, -1);
}