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[DAGCombiner] make sure we have a whole-number extract before trying to narrow a vector op (PR39511)

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The test causes a crash because we were trying to extract v4f32 to v3f32, and the
narrowing factor was then 4/3 = 1 producing a bogus narrow type.

This should fix:
https://bugs.llvm.org/show_bug.cgi?id=39511

llvm-svn: 345842
This commit is contained in:
Sanjay Patel
2018-11-01 15:41:12 +00:00
parent 29ca764492
commit c5fe3ce2ec
2 changed files with 23 additions and 1 deletions
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6
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@@ -16708,10 +16708,14 @@ static SDValue narrowExtractedVectorBinOp(SDNode *Extract, SelectionDAG &DAG) {
assert(ExtractIndex % NumElems == 0 &&
"Extract index is not a multiple of the vector length.");
EVT SrcVT = Extract->getOperand(0).getValueType();
// Bail out if this is not a proper multiple width extraction.
unsigned NumSrcElems = SrcVT.getVectorNumElements();
unsigned NarrowingRatio = NumSrcElems / NumElems;
if (NumSrcElems % NumElems != 0)
return SDValue();
// Bail out if the target does not support a narrower version of the binop.
unsigned NarrowingRatio = NumSrcElems / NumElems;
unsigned BOpcode = BinOp.getOpcode();
unsigned WideNumElts = WideBVT.getVectorNumElements();
EVT NarrowBVT = EVT::getVectorVT(*DAG.getContext(), WideBVT.getScalarType(),

18
llvm/test/CodeGen/X86/vector-narrow-binop.ll
View File

@@ -80,3 +80,21 @@ define <4 x i32> @do_not_use_256bit_op(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c,
ret <4 x i32> %sub
}
; When extracting from a vector binop, the source width should be a multiple of the destination width.
; https://bugs.llvm.org/show_bug.cgi?id=39511
define <3 x float> @PR39511(<4 x float> %t0, <3 x float>* %b) {
; SSE-LABEL: PR39511:
; SSE: # %bb.0:
; SSE-NEXT: addps {{.*}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: PR39511:
; AVX: # %bb.0:
; AVX-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%add = fadd <4 x float> %t0, <float 1.0, float 2.0, float 3.0, float 4.0>
%ext = shufflevector <4 x float> %add, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
ret <3 x float> %ext
}