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[AArch64] Add missing tests for i8 vector to half conversions.

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This commit is contained in:
Florian Hahn
2021-11-10 18:58:26 +00:00
parent fbf665a008
commit c6258a20ef
1 changed files with 88 additions and 5 deletions
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93
llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
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@@ -393,9 +393,28 @@ define <8 x i16> @bitcast_h_to_i(float, <8 x half> %a) {
ret <8 x i16> %2
}
define <4 x half> @sitofp_v4i8(<4 x i8> %a) #0 {
; CHECK-CVT-LABEL: sitofp_v4i8:
; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: shl v0.4h, v0.4h, #8
; CHECK-CVT-NEXT: sshr v0.4h, v0.4h, #8
; CHECK-CVT-NEXT: sshll v0.4s, v0.4h, #0
; CHECK-CVT-NEXT: scvtf v0.4s, v0.4s
; CHECK-CVT-NEXT: fcvtn v0.4h, v0.4s
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: sitofp_v4i8:
; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: shl v0.4h, v0.4h, #8
; CHECK-FP16-NEXT: sshr v0.4h, v0.4h, #8
; CHECK-FP16-NEXT: scvtf v0.4h, v0.4h
; CHECK-FP16-NEXT: ret
%1 = sitofp <4 x i8> %a to <4 x half>
ret <4 x half> %1
}
define <8 x half> @sitofp_i8(<8 x i8> %a) #0 {
; CHECK-LABEL: sitofp_i8:
define <8 x half> @sitofp_v8i8(<8 x i8> %a) #0 {
; CHECK-LABEL: sitofp_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
; CHECK-NEXT: sshll2 v1.4s, v0.8h, #0
@@ -410,6 +429,29 @@ define <8 x half> @sitofp_i8(<8 x i8> %a) #0 {
ret <8 x half> %1
}
define <16 x half> @sitofp_v16i8(<16 x i8> %a) #0 {
; CHECK-LABEL: sitofp_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sshll2 v1.8h, v0.16b, #0
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
; CHECK-NEXT: sshll2 v2.4s, v1.8h, #0
; CHECK-NEXT: sshll v1.4s, v1.4h, #0
; CHECK-NEXT: sshll2 v3.4s, v0.8h, #0
; CHECK-NEXT: sshll v0.4s, v0.4h, #0
; CHECK-NEXT: scvtf v2.4s, v2.4s
; CHECK-NEXT: scvtf v1.4s, v1.4s
; CHECK-NEXT: scvtf v3.4s, v3.4s
; CHECK-NEXT: scvtf v0.4s, v0.4s
; CHECK-NEXT: fcvtn v2.4h, v2.4s
; CHECK-NEXT: fcvtn v1.4h, v1.4s
; CHECK-NEXT: fcvtn v3.4h, v3.4s
; CHECK-NEXT: fcvtn v0.4h, v0.4s
; CHECK-NEXT: mov v1.d[1], v2.d[0]
; CHECK-NEXT: mov v0.d[1], v3.d[0]
; CHECK-NEXT: ret
%1 = sitofp <16 x i8> %a to <16 x half>
ret <16 x half> %1
}
define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
; CHECK-CVT-LABEL: sitofp_i16:
@@ -431,7 +473,6 @@ define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
ret <8 x half> %1
}
define <8 x half> @sitofp_i32(<8 x i32> %a) #0 {
; CHECK-LABEL: sitofp_i32:
; CHECK: // %bb.0:
@@ -465,8 +506,26 @@ define <8 x half> @sitofp_i64(<8 x i64> %a) #0 {
ret <8 x half> %1
}
define <8 x half> @uitofp_i8(<8 x i8> %a) #0 {
; CHECK-LABEL: uitofp_i8:
define <4 x half> @uitofp_v4i8(<4 x i8> %a) #0 {
; CHECK-CVT-LABEL: uitofp_v4i8:
; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: bic v0.4h, #255, lsl #8
; CHECK-CVT-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-CVT-NEXT: ucvtf v0.4s, v0.4s
; CHECK-CVT-NEXT: fcvtn v0.4h, v0.4s
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: uitofp_v4i8:
; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: bic v0.4h, #255, lsl #8
; CHECK-FP16-NEXT: ucvtf v0.4h, v0.4h
; CHECK-FP16-NEXT: ret
%1 = uitofp <4 x i8> %a to <4 x half>
ret <4 x half> %1
}
define <8 x half> @uitofp_v8i8(<8 x i8> %a) #0 {
; CHECK-LABEL: uitofp_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: ushll2 v1.4s, v0.8h, #0
@@ -481,6 +540,30 @@ define <8 x half> @uitofp_i8(<8 x i8> %a) #0 {
ret <8 x half> %1
}
define <16 x half> @uitofp_v16i8(<16 x i8> %a) #0 {
; CHECK-LABEL: uitofp_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ushll2 v1.8h, v0.16b, #0
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: ushll2 v2.4s, v1.8h, #0
; CHECK-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-NEXT: ushll2 v3.4s, v0.8h, #0
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: ucvtf v2.4s, v2.4s
; CHECK-NEXT: ucvtf v1.4s, v1.4s
; CHECK-NEXT: ucvtf v3.4s, v3.4s
; CHECK-NEXT: ucvtf v0.4s, v0.4s
; CHECK-NEXT: fcvtn v2.4h, v2.4s
; CHECK-NEXT: fcvtn v1.4h, v1.4s
; CHECK-NEXT: fcvtn v3.4h, v3.4s
; CHECK-NEXT: fcvtn v0.4h, v0.4s
; CHECK-NEXT: mov v1.d[1], v2.d[0]
; CHECK-NEXT: mov v0.d[1], v3.d[0]
; CHECK-NEXT: ret
%1 = uitofp <16 x i8> %a to <16 x half>
ret <16 x half> %1
}
define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
; CHECK-CVT-LABEL: uitofp_i16: