intel/llvm
1
0
Fork 0
mirror of https://github.com/intel/llvm.git synced 2026-01-24 08:30:34 +08:00
Code Issues Packages Projects Releases Wiki Activity

[BOLT][RISCV] Implement R_RISCV_64 (#67558)

Browse Source 
Relocation for 64-bit absolute values.
This commit is contained in:
Job Noorman
2023-09-27 14:33:59 +00:00
committed by GitHub
parent 2e9a04b985
commit cd7f1714de
2 changed files with 43 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
bolt/lib/Core/Relocation.cpp
View File

@@ -109,6 +109,7 @@ static bool isSupportedRISCV(uint64_t Type) {
case ELF::R_RISCV_HI20:
case ELF::R_RISCV_LO12_I:
case ELF::R_RISCV_LO12_S:
case ELF::R_RISCV_64:
return true;
}
}
@@ -209,6 +210,7 @@ static size_t getSizeForTypeRISCV(uint64_t Type) {
case ELF::R_RISCV_LO12_I:
case ELF::R_RISCV_LO12_S:
return 4;
case ELF::R_RISCV_64:
case ELF::R_RISCV_GOT_HI20:
// See extractValueRISCV for why this is necessary.
return 8;
@@ -364,6 +366,16 @@ static uint64_t encodeValueAArch64(uint64_t Type, uint64_t Value, uint64_t PC) {
return Value;
}
static uint64_t encodeValueRISCV(uint64_t Type, uint64_t Value, uint64_t PC) {
switch (Type) {
default:
llvm_unreachable("unsupported relocation");
case ELF::R_RISCV_64:
break;
}
return Value;
}
static uint64_t extractValueX86(uint64_t Type, uint64_t Contents, uint64_t PC) {
if (Type == ELF::R_X86_64_32S)
return SignExtend64<32>(Contents);
@@ -539,6 +551,7 @@ static uint64_t extractValueRISCV(uint64_t Type, uint64_t Contents,
return SignExtend64<8>(((Contents >> 2) & 0x1f) | ((Contents >> 5) & 0xe0));
case ELF::R_RISCV_ADD32:
case ELF::R_RISCV_SUB32:
case ELF::R_RISCV_64:
return Contents;
}
}
@@ -704,6 +717,7 @@ static bool isPCRelativeRISCV(uint64_t Type) {
case ELF::R_RISCV_HI20:
case ELF::R_RISCV_LO12_I:
case ELF::R_RISCV_LO12_S:
case ELF::R_RISCV_64:
return false;
case ELF::R_RISCV_JAL:
case ELF::R_RISCV_CALL:
@@ -756,7 +770,7 @@ uint64_t Relocation::encodeValue(uint64_t Type, uint64_t Value, uint64_t PC) {
if (Arch == Triple::aarch64)
return encodeValueAArch64(Type, Value, PC);
if (Arch == Triple::riscv64)
llvm_unreachable("not implemented");
return encodeValueRISCV(Type, Value, PC);
return encodeValueX86(Type, Value, PC);
}
@@ -844,6 +858,8 @@ bool Relocation::isPCRelative(uint64_t Type) {
uint64_t Relocation::getAbs64() {
if (Arch == Triple::aarch64)
return ELF::R_AARCH64_ABS64;
if (Arch == Triple::riscv64)
return ELF::R_RISCV_64;
return ELF::R_X86_64_64;
}

26
bolt/test/RISCV/reloc-64.s Normal file
View File

@@ -0,0 +1,26 @@
// RUN: llvm-mc -triple riscv64 -filetype=obj -o %t.o %s
// RUN: ld.lld -q -o %t %t.o
// RUN: llvm-bolt -o %t.bolt %t
// RUN: llvm-readelf -s %t.bolt | FileCheck --check-prefix=SYM %s
// RUN: llvm-readelf -x .data %t.bolt | FileCheck --check-prefix=DATA %s
// SYM: {{0+}}400000 {{.*}} _start{{$}}
// DATA: Hex dump of section '.data':
// DATA-NEXT: 00004000 00000000
.data
.globl d
.p2align 3
d:
.dword _start
.text
.globl _start
.p2align 1
_start:
ret
## Dummy relocation to force relocation mode; without it, _start will not be
## moved to a new address.
.reloc 0, R_RISCV_NONE
.size _start, .-_start