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AMDGPU: Refactor isImmOperandLegal (#155607)

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The goal is to expose more variants that can operate without
preconstructed MachineInstrs or MachineOperands.
This commit is contained in:
Matt Arsenault
2025-09-03 09:06:18 +09:00
committed by GitHub
parent 3a7d14acce
commit d7484684e5
4 changed files with 38 additions and 22 deletions
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38
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@@ -4572,19 +4572,24 @@ static bool compareMachineOp(const MachineOperand &Op0,
}
}
bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
const MachineOperand &MO) const {
const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal());
bool SIInstrInfo::isLiteralOperandLegal(const MCInstrDesc &InstDesc,
const MCOperandInfo &OpInfo) const {
if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
return true;
if (OpInfo.RegClass < 0)
if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
return false;
if (MO.isImm() && isInlineConstant(MO, OpInfo)) {
if (!isVOP3(InstDesc) || !AMDGPU::isSISrcOperand(OpInfo))
return true;
return ST.hasVOP3Literal();
}
bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
int64_t ImmVal) const {
const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
if (isInlineConstant(ImmVal, OpInfo.OperandType)) {
if (isMAI(InstDesc) && ST.hasMFMAInlineLiteralBug() &&
OpNo == (unsigned)AMDGPU::getNamedOperandIdx(InstDesc.getOpcode(),
AMDGPU::OpName::src2))
@@ -4592,13 +4597,18 @@ bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
return RI.opCanUseInlineConstant(OpInfo.OperandType);
}
if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
return false;
return isLiteralOperandLegal(InstDesc, OpInfo);
}
if (!isVOP3(InstDesc) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
return true;
bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
const MachineOperand &MO) const {
if (MO.isImm())
return isImmOperandLegal(InstDesc, OpNo, MO.getImm());
return ST.hasVOP3Literal();
assert((MO.isTargetIndex() || MO.isFI() || MO.isGlobal()) &&
"unexpected imm-like operand kind");
const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
return isLiteralOperandLegal(InstDesc, OpInfo);
}
bool SIInstrInfo::isLegalAV64PseudoImm(uint64_t Imm) const {
@@ -6268,7 +6278,7 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
return false;
}
}
} else if (AMDGPU::isSISrcOperand(InstDesc, i) &&
} else if (AMDGPU::isSISrcOperand(InstDesc.operands()[i]) &&
!isInlineConstant(Op, InstDesc.operands()[i])) {
// The same literal may be used multiple times.
if (!UsedLiteral)

6
llvm/lib/Target/AMDGPU/SIInstrInfo.h
View File

@@ -1183,6 +1183,12 @@ public:
bool isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
const MachineOperand &MO) const;
bool isLiteralOperandLegal(const MCInstrDesc &InstDesc,
const MCOperandInfo &OpInfo) const;
bool isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
int64_t ImmVal) const;
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
const MachineOperand &MO) const {
return isImmOperandLegal(MI.getDesc(), OpNo, MO);

7
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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@@ -2723,13 +2723,6 @@ bool isInlineValue(unsigned Reg) {
#undef CASE_GFXPRE11_GFX11PLUS_TO
#undef MAP_REG2REG
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
assert(OpNo < Desc.NumOperands);
unsigned OpType = Desc.operands()[OpNo].OperandType;
return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
OpType <= AMDGPU::OPERAND_SRC_LAST;
}
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo) {
assert(OpNo < Desc.NumOperands);
unsigned OpType = Desc.operands()[OpNo].OperandType;

9
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
View File

@@ -1590,7 +1590,14 @@ bool isInlineValue(unsigned Reg);
/// Is this an AMDGPU specific source operand? These include registers,
/// inline constants, literals and mandatory literals (KImm).
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
constexpr bool isSISrcOperand(const MCOperandInfo &OpInfo) {
return OpInfo.OperandType >= AMDGPU::OPERAND_SRC_FIRST &&
OpInfo.OperandType <= AMDGPU::OPERAND_SRC_LAST;
}
constexpr bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
return isSISrcOperand(Desc.operands()[OpNo]);
}
/// Is this a KImm operand?
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);