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[RISCV] Sink more common code from RVInst/RVInst16 into RVInstCommon. NFC
Reviewed By: wangpc Differential Revision: https://reviews.llvm.org/D155787
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@@ -156,9 +156,15 @@ def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>;
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def OPC_OP_P : RISCVOpcode<"OP_P", 0b1110111>;
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def OPC_CUSTOM_3 : RISCVOpcode<"CUSTOM_3", 0b1111011>;
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class RVInstCommon<InstFormat format> : Instruction {
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class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
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list<dag> pattern, InstFormat format> : Instruction {
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let Namespace = "RISCV";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = opcodestr # "\t" # argstr;
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let Pattern = pattern;
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let TSFlags{4-0} = format.Value;
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// Defaults
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@@ -210,7 +216,7 @@ class RVInstCommon<InstFormat format> : Instruction {
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class RVInst<dag outs, dag ins, string opcodestr, string argstr,
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list<dag> pattern, InstFormat format>
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: RVInstCommon<format> {
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: RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
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field bits<32> Inst;
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// SoftFail is a field the disassembler can use to provide a way for
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// instructions to not match without killing the whole decode process. It is
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@@ -222,11 +228,6 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
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bits<7> Opcode = 0;
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let Inst{6-0} = Opcode;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = opcodestr # "\t" # argstr;
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let Pattern = pattern;
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}
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// Pseudo instructions
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@@ -12,7 +12,7 @@
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class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
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list<dag> pattern, InstFormat format>
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: RVInstCommon<format> {
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: RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
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field bits<16> Inst;
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// SoftFail is a field the disassembler can use to provide a way for
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// instructions to not match without killing the whole decode process. It is
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@@ -22,11 +22,6 @@ class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
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let Size = 2;
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bits<2> Opcode = 0;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = opcodestr # "\t" # argstr;
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let Pattern = pattern;
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}
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class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
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