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[AMDGPU] Pre-commit test for D111126 (NFC)
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Carl Ritson
126
llvm/test/CodeGen/AMDGPU/artificial-terminators.mir
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126
llvm/test/CodeGen/AMDGPU/artificial-terminators.mir
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@@ -0,0 +1,126 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=machine-sink -o - %s | FileCheck %s
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---
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name: func0
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr7'
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body: |
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; CHECK-LABEL: name: func0
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr4, $vgpr6
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr6
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr4
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; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY1]], [[COPY]], 0, implicit $exec
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 31
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; CHECK-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 killed [[S_MOV_B32_]], [[V_ADD_U32_e64_]], implicit $exec
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; CHECK-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], killed [[V_LSHRREV_B32_e64_]], 0, implicit $exec
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; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
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; CHECK-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[S_MOV_B32_1]], killed [[V_ADD_U32_e64_1]], implicit $exec
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; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 30
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; CHECK-NEXT: [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 killed [[S_MOV_B32_2]], [[V_ASHRREV_I32_e64_]], implicit $exec
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; CHECK-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ASHRREV_I32_e64_]], killed [[V_LSHRREV_B32_e64_1]], 0, implicit $exec
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; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_3]]
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; CHECK-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 killed [[V_ADD_U32_e64_2]], killed [[COPY2]], implicit $exec
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; CHECK-NEXT: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_ASHRREV_I32_e64_]], killed [[V_AND_B32_e32_]], 0, implicit $exec
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; CHECK-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 4
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; CHECK-NEXT: [[V_ADD_U32_e64_3:%[0-9]+]]:vgpr_32 = nsw V_ADD_U32_e64 killed [[V_SUB_U32_e64_]], killed [[S_MOV_B32_4]], 0, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.5(0x30000000), %bb.2(0x50000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[V_ADD_U32_e64_3]], [[S_MOV_B32_1]], implicit $exec
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; CHECK-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 $exec_lo, [[V_CMP_LT_I32_e64_]], implicit-def $scc
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; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.2, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.5:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[V_CMP_LT_I32_e64_]]
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; CHECK-NEXT: S_BRANCH %bb.4
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 1
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; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[V_ADD_U32_e64_3]], killed [[S_MOV_B32_5]], implicit $exec
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; CHECK-NEXT: [[S_XOR_B32_1:%[0-9]+]]:sreg_32 = S_XOR_B32 $exec_lo, [[V_CMP_EQ_U32_e64_]], implicit-def $scc
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; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_LT_I32_e64_]], [[V_CMP_EQ_U32_e64_]], implicit-def $scc
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; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_XOR_B32_1]]
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_BRANCH %bb.4
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[COPY3]], %bb.5, [[S_OR_B32_]], %bb.2, [[S_OR_B32_]], %bb.3
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; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[PHI]], implicit-def $scc
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1(0x80000000); %bb.1(100.00%)
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liveins: $vgpr4, $vgpr6
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%7:vgpr_32 = COPY $vgpr6
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%5:vgpr_32 = COPY $vgpr4
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%9:vgpr_32 = V_ADD_U32_e64 %5:vgpr_32, %7:vgpr_32, 0, implicit $exec
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%11:sreg_32 = S_MOV_B32 31
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%12:vgpr_32 = V_LSHRREV_B32_e64 killed %11:sreg_32, %9:vgpr_32, implicit $exec
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%13:vgpr_32 = V_ADD_U32_e64 %9:vgpr_32, killed %12:vgpr_32, 0, implicit $exec
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%14:sreg_32 = S_MOV_B32 1
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%15:vgpr_32 = V_ASHRREV_I32_e64 %14:sreg_32, killed %13:vgpr_32, implicit $exec
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%16:sreg_32 = S_MOV_B32 30
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%17:vgpr_32 = V_LSHRREV_B32_e64 killed %16:sreg_32, %15:vgpr_32, implicit $exec
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%18:vgpr_32 = V_ADD_U32_e64 %15:vgpr_32, killed %17:vgpr_32, 0, implicit $exec
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%19:sreg_32 = S_MOV_B32 -4
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%21:vgpr_32 = COPY %19:sreg_32
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%20:vgpr_32 = V_AND_B32_e32 killed %18:vgpr_32, killed %21:vgpr_32, implicit $exec
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%22:vgpr_32 = V_SUB_U32_e64 %15:vgpr_32, killed %20:vgpr_32, 0, implicit $exec
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%23:sreg_32 = S_MOV_B32 4
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%0:vgpr_32 = nsw V_ADD_U32_e64 killed %22:vgpr_32, killed %23:sreg_32, 0, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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; predecessors: %bb.0
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successors: %bb.4(0x30000000), %bb.2(0x50000000); %bb.4(37.50%), %bb.2(62.50%)
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%25:sreg_32 = V_CMP_LT_I32_e64 %0:vgpr_32, %14:sreg_32, implicit $exec
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%28:sreg_32 = S_XOR_B32 $exec_lo, %25:sreg_32, implicit-def $scc
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%33:sreg_32 = COPY %25:sreg_32
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$exec_lo = S_MOV_B32_term %28:sreg_32
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S_CBRANCH_EXECZ %bb.4, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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; predecessors: %bb.1
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successors: %bb.4(0x40000000), %bb.3(0x40000000); %bb.4(50.00%), %bb.3(50.00%)
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%26:sreg_32 = S_MOV_B32 1
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%27:sreg_32 = V_CMP_EQ_U32_e64 %0:vgpr_32, killed %26:sreg_32, implicit $exec
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%31:sreg_32 = S_XOR_B32 $exec_lo, %27:sreg_32, implicit-def $scc
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%34:sreg_32 = S_OR_B32 %25:sreg_32, %27:sreg_32, implicit-def $scc
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$exec_lo = S_MOV_B32_term %31:sreg_32
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S_CBRANCH_EXECZ %bb.4, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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; predecessors: %bb.2
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successors: %bb.4(0x80000000); %bb.4(100.00%)
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S_BRANCH %bb.4
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bb.4:
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; predecessors: %bb.1, %bb.2, %bb.3
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%35:sreg_32 = PHI %33:sreg_32, %bb.1, %34:sreg_32, %bb.2, %34:sreg_32, %bb.3
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$exec_lo = S_OR_B32 $exec_lo, %35:sreg_32, implicit-def $scc
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S_ENDPGM 0
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...
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