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https://github.com/intel/llvm.git
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[LLDB][LoongArch] Add branch instructions for EmulateInstructionLoongArch
Add conditional and unconditional branch instructions for loongarch64. Note that this does not include floating-point branch instructions, that will come in a later patch. Reviewed By: SixWeining, DavidSpickett Differential Revision: https://reviews.llvm.org/D139833
This commit is contained in:
Hui Li
Weining Lu
@@ -33,8 +33,30 @@ namespace lldb_private {
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EmulateInstructionLoongArch::Opcode *
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EmulateInstructionLoongArch::GetOpcodeForInstruction(uint32_t inst) {
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// TODO: Add the mask of jump instruction.
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// TODO: Add the mask for other instruction.
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static EmulateInstructionLoongArch::Opcode g_opcodes[] = {
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{0xfc000000, 0x40000000, &EmulateInstructionLoongArch::EmulateBEQZ,
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"beqz rj, offs21"},
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{0xfc000000, 0x44000000, &EmulateInstructionLoongArch::EmulateBNEZ,
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"bnez rj, offs21"},
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{0xfc000000, 0x4c000000, &EmulateInstructionLoongArch::EmulateJIRL,
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"jirl rd, rj, offs16"},
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{0xfc000000, 0x50000000, &EmulateInstructionLoongArch::EmulateB,
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" b offs26"},
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{0xfc000000, 0x54000000, &EmulateInstructionLoongArch::EmulateBL,
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"bl offs26"},
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{0xfc000000, 0x58000000, &EmulateInstructionLoongArch::EmulateBEQ,
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"beq rj, rd, offs16"},
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{0xfc000000, 0x5c000000, &EmulateInstructionLoongArch::EmulateBNE,
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"bne rj, rd, offs16"},
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{0xfc000000, 0x60000000, &EmulateInstructionLoongArch::EmulateBLT,
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"blt rj, rd, offs16"},
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{0xfc000000, 0x64000000, &EmulateInstructionLoongArch::EmulateBGE,
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"bge rj, rd, offs16"},
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{0xfc000000, 0x68000000, &EmulateInstructionLoongArch::EmulateBLTU,
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"bltu rj, rd, offs16"},
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{0xfc000000, 0x6c000000, &EmulateInstructionLoongArch::EmulateBGEU,
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"bgeu rj, rd, offs16"},
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{0x00000000, 0x00000000, &EmulateInstructionLoongArch::EmulateNonJMP,
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"NonJMP"}};
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static const size_t num_loongarch_opcodes = std::size(g_opcodes);
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@@ -176,6 +198,339 @@ bool EmulateInstructionLoongArch::SupportsThisArch(const ArchSpec &arch) {
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return arch.GetTriple().isLoongArch();
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}
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bool EmulateInstructionLoongArch::EmulateBEQZ(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateBEQZ64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateBNEZ(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateBNEZ64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateJIRL(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateJIRL64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateB(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateB64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateBL(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateBL64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateBEQ(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateBEQ64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateBNE(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateJIRL64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateBLT(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateBLT64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateBGE(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateBGE64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateBLTU(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateBLTU64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateBGEU(uint32_t inst) {
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if (IsLoongArch64())
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return EmulateBGEU64(inst);
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else
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return false;
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}
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bool EmulateInstructionLoongArch::EmulateNonJMP(uint32_t inst) { return false; }
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// beqz rj, offs21
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// if GR[rj] == 0:
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// PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateBEQZ64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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bool success = false;
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uint32_t rj = Bits32(inst, 9, 5);
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uint64_t rj_val;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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uint32_t offs21 = Bits32(inst, 25, 10) + (Bits32(inst, 4, 0) << 16);
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rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
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if (!success)
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return false;
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if (rj_val == 0) {
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imm_sign_extend = llvm::SignExtend64<23>(offs21 << 2);
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next_pc = pc + imm_sign_extend;
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return WritePC(next_pc);
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} else
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return WritePC(pc + 4);
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}
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// bnez rj, offs21
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// if GR[rj] != 0:
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// PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateBNEZ64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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bool success = false;
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uint32_t rj = Bits32(inst, 9, 5);
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uint64_t rj_val;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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uint32_t offs21 = Bits32(inst, 25, 10) + (Bits32(inst, 4, 0) << 16);
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rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
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if (!success)
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return false;
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if (rj_val != 0) {
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imm_sign_extend = llvm::SignExtend64<23>(offs21 << 2);
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next_pc = pc + imm_sign_extend;
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return WritePC(next_pc);
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} else
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return WritePC(pc + 4);
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}
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// jirl rd, rj, offs16
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// GR[rd] = PC + 4
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// PC = GR[rj] + SignExtend({offs16, 2'b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateJIRL64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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RegisterValue value;
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uint32_t rj = Bits32(inst, 9, 5);
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uint32_t rd = Bits32(inst, 4, 0);
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bool success = false;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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EmulateInstruction::Context ctx;
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if (!WriteRegisterUnsigned(ctx, eRegisterKindLLDB, rd, pc + 4))
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return false;
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if (!ReadRegister(eRegisterKindLLDB, rj, value))
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return false;
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imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
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next_pc = value.GetAsUInt64() + imm_sign_extend;
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return WritePC(next_pc);
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}
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// b offs26
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// PC = PC + SignExtend({offs26, 2' b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateB64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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bool success = false;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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uint32_t offs26 = Bits32(inst, 25, 10) + (Bits32(inst, 9, 0) << 16);
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imm_sign_extend = llvm::SignExtend64<28>(offs26 << 2);
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next_pc = pc + imm_sign_extend;
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return WritePC(next_pc);
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}
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// bl offs26
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// GR[1] = PC + 4
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// PC = PC + SignExtend({offs26, 2'b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateBL64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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bool success = false;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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EmulateInstruction::Context ctx;
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if (!WriteRegisterUnsigned(ctx, eRegisterKindLLDB, gpr_r1_loongarch, pc + 4))
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return false;
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uint32_t offs26 = Bits32(inst, 25, 10) + (Bits32(inst, 9, 0) << 16);
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imm_sign_extend = llvm::SignExtend64<28>(offs26 << 2);
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next_pc = pc + imm_sign_extend;
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return WritePC(next_pc);
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}
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// beq rj, rd, offs16
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// if GR[rj] == GR[rd]:
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// PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateBEQ64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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bool success = false;
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uint32_t rj = Bits32(inst, 9, 5);
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uint32_t rd = Bits32(inst, 4, 0);
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uint64_t rj_val, rd_val;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
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if (!success)
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return false;
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rd_val = ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
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if (!success)
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return false;
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if (rj_val == rd_val) {
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imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
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next_pc = pc + imm_sign_extend;
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return WritePC(next_pc);
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} else
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return WritePC(pc + 4);
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}
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// bne rj, rd, offs16
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// if GR[rj] != GR[rd]:
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// PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateBNE64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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bool success = false;
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uint32_t rj = Bits32(inst, 9, 5);
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uint32_t rd = Bits32(inst, 4, 0);
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uint64_t rj_val, rd_val;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
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if (!success)
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return false;
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rd_val = ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
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if (!success)
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return false;
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if (rj_val != rd_val) {
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imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
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next_pc = pc + imm_sign_extend;
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return WritePC(next_pc);
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} else
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return WritePC(pc + 4);
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}
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// blt rj, rd, offs16
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// if signed(GR[rj]) < signed(GR[rd]):
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// PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateBLT64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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bool success = false;
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uint32_t rj = Bits32(inst, 9, 5);
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uint32_t rd = Bits32(inst, 4, 0);
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int64_t rj_val, rd_val;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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rj_val = (int64_t)ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
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if (!success)
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return false;
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rd_val = (int64_t)ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
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if (!success)
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return false;
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if (rj_val < rd_val) {
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imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
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next_pc = pc + imm_sign_extend;
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return WritePC(next_pc);
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} else
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return WritePC(pc + 4);
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}
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// bge rj, rd, offs16
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// if signed(GR[rj]) >= signed(GR[rd]):
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// PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateBGE64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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bool success = false;
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uint32_t rj = Bits32(inst, 9, 5);
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uint32_t rd = Bits32(inst, 4, 0);
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int64_t rj_val, rd_val;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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rj_val = (int64_t)ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
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if (!success)
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return false;
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rd_val = (int64_t)ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
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if (!success)
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return false;
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if (rj_val >= rd_val) {
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imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
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next_pc = pc + imm_sign_extend;
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return WritePC(next_pc);
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} else
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return WritePC(pc + 4);
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}
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// bltu rj, rd, offs16
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// if unsigned(GR[rj]) < unsigned(GR[rd]):
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// PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateBLTU64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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bool success = false;
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uint32_t rj = Bits32(inst, 9, 5);
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uint32_t rd = Bits32(inst, 4, 0);
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uint64_t rj_val, rd_val;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
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if (!success)
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return false;
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rd_val = ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
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if (!success)
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return false;
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if (rj_val < rd_val) {
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imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
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next_pc = pc + imm_sign_extend;
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return WritePC(next_pc);
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} else
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return WritePC(pc + 4);
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}
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// bgeu rj, rd, offs16
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// if unsigned(GR[rj]) >= unsigned(GR[rd]):
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// PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
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bool EmulateInstructionLoongArch::EmulateBGEU64(uint32_t inst) {
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uint64_t next_pc, imm_sign_extend;
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bool success = false;
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uint32_t rj = Bits32(inst, 9, 5);
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uint32_t rd = Bits32(inst, 4, 0);
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uint64_t rj_val, rd_val;
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uint64_t pc = ReadPC(&success);
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if (!success)
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return false;
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rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
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if (!success)
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return false;
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rd_val = ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
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if (!success)
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return false;
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if (rj_val >= rd_val) {
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imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
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next_pc = pc + imm_sign_extend;
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return WritePC(next_pc);
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} else
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return WritePC(pc + 4);
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}
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} // namespace lldb_private
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@@ -38,8 +38,9 @@ public:
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static void Terminate();
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public:
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EmulateInstructionLoongArch(const ArchSpec &arch)
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: EmulateInstruction(arch) {}
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EmulateInstructionLoongArch(const ArchSpec &arch) : EmulateInstruction(arch) {
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m_arch_subtype = arch.GetMachine();
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}
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llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
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@@ -57,6 +58,7 @@ public:
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uint32_t reg_num) override;
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lldb::addr_t ReadPC(bool *success);
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bool WritePC(lldb::addr_t pc);
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bool IsLoongArch64() { return m_arch_subtype == llvm::Triple::loongarch64; }
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private:
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struct Opcode {
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@@ -66,9 +68,33 @@ private:
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const char *name;
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};
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llvm::Triple::ArchType m_arch_subtype;
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Opcode *GetOpcodeForInstruction(uint32_t inst);
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bool EmulateBEQZ(uint32_t inst);
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bool EmulateBNEZ(uint32_t inst);
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bool EmulateJIRL(uint32_t inst);
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bool EmulateB(uint32_t inst);
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bool EmulateBL(uint32_t inst);
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bool EmulateBEQ(uint32_t inst);
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bool EmulateBNE(uint32_t inst);
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bool EmulateBLT(uint32_t inst);
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bool EmulateBGE(uint32_t inst);
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bool EmulateBLTU(uint32_t inst);
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bool EmulateBGEU(uint32_t inst);
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bool EmulateNonJMP(uint32_t inst);
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bool EmulateBEQZ64(uint32_t inst);
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bool EmulateBNEZ64(uint32_t inst);
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bool EmulateJIRL64(uint32_t inst);
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bool EmulateB64(uint32_t inst);
|
||||
bool EmulateBL64(uint32_t inst);
|
||||
bool EmulateBEQ64(uint32_t inst);
|
||||
bool EmulateBNE64(uint32_t inst);
|
||||
bool EmulateBLT64(uint32_t inst);
|
||||
bool EmulateBGE64(uint32_t inst);
|
||||
bool EmulateBLTU64(uint32_t inst);
|
||||
bool EmulateBGEU64(uint32_t inst);
|
||||
};
|
||||
|
||||
} // namespace lldb_private
|
||||
|
||||
Reference in New Issue
Block a user