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[Clang][x86]: allow PCLMULQDQ intrinsics to be used in constexpr (#169214)

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Resolves #168741
This commit is contained in:
Ahmed Nour
2025-12-15 12:27:17 +02:00
committed by GitHub
parent f024026a21
commit ed79fd714f
5 changed files with 237 additions and 4 deletions
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9
clang/include/clang/Basic/BuiltinsX86.td
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@@ -426,15 +426,18 @@ let Features = "avx512f,gfni", Attributes = [NoThrow, Const, Constexpr, Required
def vgf2p8mulb_v64qi : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>)">;
}
let Features = "pclmul", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
let Features = "pclmul",
Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<128>] in {
def pclmulqdq128 : X86Builtin<"_Vector<2, long long int>(_Vector<2, long long int>, _Vector<2, long long int>, _Constant char)">;
}
let Features = "vpclmulqdq", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
let Features = "vpclmulqdq",
Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<256>] in {
def pclmulqdq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Constant char)">;
}
let Features = "avx512f,vpclmulqdq", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
let Features = "avx512f,vpclmulqdq",
Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in {
def pclmulqdq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Constant char)">;
}

64
clang/lib/AST/ByteCode/InterpBuiltin.cpp
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@@ -2757,6 +2757,65 @@ static bool interp__builtin_ia32_addsub(InterpState &S, CodePtr OpPC,
return true;
}
static bool interp__builtin_ia32_pclmulqdq(InterpState &S, CodePtr OpPC,
const CallExpr *Call) {
// PCLMULQDQ: carry-less multiplication of selected 64-bit halves
// imm8 bit 0: selects lower (0) or upper (1) 64 bits of first operand
// imm8 bit 4: selects lower (0) or upper (1) 64 bits of second operand
assert(Call->getArg(0)->getType()->isVectorType() &&
Call->getArg(1)->getType()->isVectorType());
// Extract imm8 argument
APSInt Imm8 = popToAPSInt(S, Call->getArg(2));
bool SelectUpperA = (Imm8 & 0x01) != 0;
bool SelectUpperB = (Imm8 & 0x10) != 0;
const Pointer &RHS = S.Stk.pop<Pointer>();
const Pointer &LHS = S.Stk.pop<Pointer>();
const Pointer &Dst = S.Stk.peek<Pointer>();
const auto *VT = Call->getArg(0)->getType()->castAs<VectorType>();
PrimType ElemT = *S.getContext().classify(VT->getElementType());
unsigned NumElems = VT->getNumElements();
const auto *DestVT = Call->getType()->castAs<VectorType>();
PrimType DestElemT = *S.getContext().classify(DestVT->getElementType());
bool DestUnsigned = Call->getType()->isUnsignedIntegerOrEnumerationType();
// Process each 128-bit lane (2 elements at a time)
for (unsigned Lane = 0; Lane < NumElems; Lane += 2) {
APSInt A0, A1, B0, B1;
INT_TYPE_SWITCH_NO_BOOL(ElemT, {
A0 = LHS.elem<T>(Lane + 0).toAPSInt();
A1 = LHS.elem<T>(Lane + 1).toAPSInt();
B0 = RHS.elem<T>(Lane + 0).toAPSInt();
B1 = RHS.elem<T>(Lane + 1).toAPSInt();
});
// Select the appropriate 64-bit values based on imm8
APInt A = SelectUpperA ? A1 : A0;
APInt B = SelectUpperB ? B1 : B0;
// Extend both operands to 128 bits for carry-less multiplication
APInt A128 = A.zext(128);
APInt B128 = B.zext(128);
// Use APIntOps::clmul for carry-less multiplication
APInt Result = llvm::APIntOps::clmul(A128, B128);
// Split the 128-bit result into two 64-bit halves
APSInt ResultLow(Result.extractBits(64, 0), DestUnsigned);
APSInt ResultHigh(Result.extractBits(64, 64), DestUnsigned);
INT_TYPE_SWITCH_NO_BOOL(DestElemT, {
Dst.elem<T>(Lane + 0) = static_cast<T>(ResultLow);
Dst.elem<T>(Lane + 1) = static_cast<T>(ResultHigh);
});
}
Dst.initializeAllElements();
return true;
}
static bool interp__builtin_elementwise_triop_fp(
InterpState &S, CodePtr OpPC, const CallExpr *Call,
llvm::function_ref<APFloat(const APFloat &, const APFloat &,
@@ -4787,6 +4846,11 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
return llvm::APIntOps::muluExtended(LoLHS, LoRHS);
});
case clang::X86::BI__builtin_ia32_pclmulqdq128:
case clang::X86::BI__builtin_ia32_pclmulqdq256:
case clang::X86::BI__builtin_ia32_pclmulqdq512:
return interp__builtin_ia32_pclmulqdq(S, OpPC, Call);
case Builtin::BI__builtin_elementwise_fma:
return interp__builtin_elementwise_triop_fp(
S, OpPC, Call,

55
clang/lib/AST/ExprConstant.cpp
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@@ -13785,6 +13785,61 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr *E) {
}
return Success(APValue(ResultElements.data(), ResultElements.size()), E);
}
case clang::X86::BI__builtin_ia32_pclmulqdq128:
case clang::X86::BI__builtin_ia32_pclmulqdq256:
case clang::X86::BI__builtin_ia32_pclmulqdq512: {
// PCLMULQDQ: carry-less multiplication of selected 64-bit halves
// imm8 bit 0: selects lower (0) or upper (1) 64 bits of first operand
// imm8 bit 4: selects lower (0) or upper (1) 64 bits of second operand
APValue SourceLHS, SourceRHS;
if (!EvaluateAsRValue(Info, E->getArg(0), SourceLHS) ||
!EvaluateAsRValue(Info, E->getArg(1), SourceRHS))
return false;
APSInt Imm8;
if (!EvaluateInteger(E->getArg(2), Imm8, Info))
return false;
// Extract bits 0 and 4 from imm8
bool SelectUpperA = (Imm8 & 0x01) != 0;
bool SelectUpperB = (Imm8 & 0x10) != 0;
unsigned NumElems = SourceLHS.getVectorLength();
SmallVector<APValue, 8> ResultElements;
ResultElements.reserve(NumElems);
QualType DestEltTy = E->getType()->castAs<VectorType>()->getElementType();
bool DestUnsigned = DestEltTy->isUnsignedIntegerOrEnumerationType();
// Process each 128-bit lane
for (unsigned Lane = 0; Lane < NumElems; Lane += 2) {
// Get the two 64-bit halves of the first operand
APSInt A0 = SourceLHS.getVectorElt(Lane + 0).getInt();
APSInt A1 = SourceLHS.getVectorElt(Lane + 1).getInt();
// Get the two 64-bit halves of the second operand
APSInt B0 = SourceRHS.getVectorElt(Lane + 0).getInt();
APSInt B1 = SourceRHS.getVectorElt(Lane + 1).getInt();
// Select the appropriate 64-bit values based on imm8
APInt A = SelectUpperA ? A1 : A0;
APInt B = SelectUpperB ? B1 : B0;
// Extend both operands to 128 bits for carry-less multiplication
APInt A128 = A.zext(128);
APInt B128 = B.zext(128);
// Use APIntOps::clmul for carry-less multiplication
APInt Result = llvm::APIntOps::clmul(A128, B128);
// Split the 128-bit result into two 64-bit halves
APSInt ResultLow(Result.extractBits(64, 0), DestUnsigned);
APSInt ResultHigh(Result.extractBits(64, 64), DestUnsigned);
ResultElements.push_back(APValue(ResultLow));
ResultElements.push_back(APValue(ResultHigh));
}
return Success(APValue(ResultElements.data(), ResultElements.size()), E);
}
case Builtin::BI__builtin_elementwise_fshl:
case Builtin::BI__builtin_elementwise_fshr: {
APValue SourceHi, SourceLo, SourceShift;

35
clang/test/CodeGen/X86/pclmul-builtins.c
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@@ -1,9 +1,42 @@
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +pclmul -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -x c++ -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +pclmul -emit-llvm -o - -std=c++11 | FileCheck %s
// RUN: %clang_cc1 -x c++ -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +pclmul -emit-llvm -o - -std=c++11 -fexperimental-new-constant-interpreter | FileCheck %s
#include <wmmintrin.h>
#include "builtin_test_helpers.h"
__m128i test_mm_clmulepi64_si128(__m128i a, __m128i b) {
// CHECK: @llvm.x86.pclmulqdq
return _mm_clmulepi64_si128(a, b, 0);
}
// Test constexpr evaluation for _mm_clmulepi64_si128
// imm8=0x00: lower 64 bits of both operands
// Test case: 0x1 * 0x3 = 0x3 (carry-less multiplication)
TEST_CONSTEXPR(match_m128i(_mm_clmulepi64_si128(((__m128i){0x1ULL, 0x0ULL}), ((__m128i){0x3ULL, 0x0ULL}), 0x00), 0x3ULL, 0x0ULL));
// imm8=0x01: upper 64 bits of first operand, lower 64 bits of second
TEST_CONSTEXPR(match_m128i(_mm_clmulepi64_si128(((__m128i){0x0ULL, 0x1ULL}), ((__m128i){0x3ULL, 0x0ULL}), 0x01), 0x3ULL, 0x0ULL));
// imm8=0x10: lower 64 bits of first operand, upper 64 bits of second
TEST_CONSTEXPR(match_m128i(_mm_clmulepi64_si128(((__m128i){0x1ULL, 0x0ULL}), ((__m128i){0x0ULL, 0x3ULL}), 0x10), 0x3ULL, 0x0ULL));
// imm8=0x11: upper 64 bits of both operands
TEST_CONSTEXPR(match_m128i(_mm_clmulepi64_si128(((__m128i){0x0ULL, 0x1ULL}), ((__m128i){0x0ULL, 0x3ULL}), 0x11), 0x3ULL, 0x0ULL));
// Test cases with non-zero upper 64-bit results
// imm8=0x00: lower 64 bits of both operands
// 0x8000000000000000 * 0x2 = result with upper bits set
TEST_CONSTEXPR(match_m128i(_mm_clmulepi64_si128(((__m128i){(long long)0x8000000000000000ULL, 0x0ULL}), ((__m128i){0x2ULL, 0x0ULL}), 0x00), 0x0ULL, 0x1ULL));
// imm8=0x01: upper 64 bits of first operand, lower 64 bits of second
// 0xFFFFFFFFFFFFFFFF * 0x2 = result with upper bits set
TEST_CONSTEXPR(match_m128i(_mm_clmulepi64_si128(((__m128i){0x0ULL, (long long)0xFFFFFFFFFFFFFFFFULL}), ((__m128i){0x2ULL, 0x0ULL}), 0x01), 0xFFFFFFFFFFFFFFFEULL, 0x1ULL));
// imm8=0x10: lower 64 bits of first operand, upper 64 bits of second
// 0x1000000000000000 * 0x10 = result with upper bits set
TEST_CONSTEXPR(match_m128i(_mm_clmulepi64_si128(((__m128i){(long long)0x1000000000000000ULL, 0x0ULL}), ((__m128i){0x0ULL, 0x10ULL}), 0x10), 0x0ULL, 0x1ULL));
// imm8=0x11: upper 64 bits of both operands
// 0x8000000000000001 * 0x8000000000000001 = result with upper bits set
TEST_CONSTEXPR(match_m128i(_mm_clmulepi64_si128(((__m128i){0x0ULL, (long long)0x8000000000000001ULL}), ((__m128i){0x0ULL, (long long)0x8000000000000001ULL}), 0x11), 0x1ULL, 0x4000000000000000ULL));

78
clang/test/CodeGen/X86/vpclmulqdq-builtins.c
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@@ -1,17 +1,95 @@
// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +vpclmulqdq -emit-llvm -o - | FileCheck %s --check-prefix AVX
// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +vpclmulqdq -target-feature +avx512f -emit-llvm -o - | FileCheck %s --check-prefixes AVX,AVX512
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +vpclmulqdq -emit-llvm -o - -std=c++11 | FileCheck %s --check-prefix AVX
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +vpclmulqdq -target-feature +avx512f -emit-llvm -o - -std=c++11 | FileCheck %s --check-prefixes AVX,AVX512
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +vpclmulqdq -emit-llvm -o - -std=c++11 -fexperimental-new-constant-interpreter | FileCheck %s --check-prefix AVX
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +vpclmulqdq -target-feature +avx512f -emit-llvm -o - -std=c++11 -fexperimental-new-constant-interpreter | FileCheck %s --check-prefixes AVX,AVX512
#include <immintrin.h>
#include "builtin_test_helpers.h"
__m256i test_mm256_clmulepi64_epi128(__m256i A, __m256i B) {
// AVX: @llvm.x86.pclmulqdq.256
return _mm256_clmulepi64_epi128(A, B, 0);
}
// Test constexpr evaluation for _mm256_clmulepi64_epi128
// Each 128-bit lane is processed independently
// Basic test cases for all imm8 values (0x00, 0x01, 0x10, 0x11)
// imm8=0x00: lower 64 bits of both operands in each lane
TEST_CONSTEXPR(match_m256i(_mm256_clmulepi64_epi128(((__m256i){0x1ULL, 0x0ULL, 0x2ULL, 0x0ULL}), ((__m256i){0x3ULL, 0x0ULL, 0x5ULL, 0x0ULL}), 0x00), 0x3ULL, 0x0ULL, 0xaULL, 0x0ULL));
// imm8=0x01: upper 64 bits of first operand, lower 64 bits of second in each lane
TEST_CONSTEXPR(match_m256i(_mm256_clmulepi64_epi128(((__m256i){0x0ULL, 0x1ULL, 0x0ULL, 0x2ULL}), ((__m256i){0x3ULL, 0x0ULL, 0x5ULL, 0x0ULL}), 0x01), 0x3ULL, 0x0ULL, 0xaULL, 0x0ULL));
// imm8=0x10: lower 64 bits of first operand, upper 64 bits of second in each lane
TEST_CONSTEXPR(match_m256i(_mm256_clmulepi64_epi128(((__m256i){0x1ULL, 0x0ULL, 0x2ULL, 0x0ULL}), ((__m256i){0x0ULL, 0x3ULL, 0x0ULL, 0x5ULL}), 0x10), 0x3ULL, 0x0ULL, 0xaULL, 0x0ULL));
// imm8=0x11: upper 64 bits of both operands in each lane
TEST_CONSTEXPR(match_m256i(_mm256_clmulepi64_epi128(((__m256i){0x0ULL, 0x1ULL, 0x0ULL, 0x2ULL}), ((__m256i){0x0ULL, 0x3ULL, 0x0ULL, 0x5ULL}), 0x11), 0x3ULL, 0x0ULL, 0xaULL, 0x0ULL));
// Complex test cases with edge values and non-zero upper 64-bit results
// Test with high bit set (0x8000000000000000) - produces result with upper bits
TEST_CONSTEXPR(match_m256i(_mm256_clmulepi64_epi128(((__m256i){(long long)0x8000000000000000ULL, 0x0ULL, (long long)0x8000000000000000ULL, 0x0ULL}), ((__m256i){0x2ULL, 0x0ULL, 0x4ULL, 0x0ULL}), 0x00), 0x0ULL, 0x1ULL, 0x0ULL, 0x2ULL));
// Test with all bits set (0xFFFFFFFFFFFFFFFF) - maximum value
// imm8=0x01: upper(A) * lower(B) for each 128-bit lane
// For lane 0: upper(0xFFFFFFFFFFFFFFFF) * lower(0x2)
// For lane 1: upper(0xFFFFFFFFFFFFFFFF) * lower(0x3)
// Note: This test case removed due to complexity - using simpler edge cases instead
// Test with large values that cause carry propagation
TEST_CONSTEXPR(match_m256i(_mm256_clmulepi64_epi128(((__m256i){(long long)0x1000000000000000ULL, 0x0ULL, (long long)0x2000000000000000ULL, 0x0ULL}), ((__m256i){0x0ULL, 0x10ULL, 0x0ULL, 0x20ULL}), 0x10), 0x0ULL, 0x1ULL, 0x0ULL, 0x4ULL));
// Test with values that produce results in upper 64 bits
TEST_CONSTEXPR(match_m256i(_mm256_clmulepi64_epi128(((__m256i){0x0ULL, (long long)0x8000000000000001ULL, 0x0ULL, (long long)0x8000000000000001ULL}), ((__m256i){0x0ULL, (long long)0x8000000000000001ULL, 0x0ULL, (long long)0x8000000000000001ULL}), 0x11), 0x1ULL, 0x4000000000000000ULL, 0x1ULL, 0x4000000000000000ULL));
// Test with polynomial-like values (common in CRC/GCM)
// x^63 + x^62 + ... + x + 1 = 0xFFFFFFFFFFFFFFFF
// x^64 = 0x10000000000000000 (represented as upper 64 bits = 1)
TEST_CONSTEXPR(match_m256i(_mm256_clmulepi64_epi128(((__m256i){0x1ULL, 0x0ULL, (long long)0xFFFFFFFFFFFFFFFFULL, 0x0ULL}), ((__m256i){(long long)0xFFFFFFFFFFFFFFFFULL, 0x0ULL, 0x1ULL, 0x0ULL}), 0x00), (long long)0xFFFFFFFFFFFFFFFFULL, 0x0ULL, (long long)0xFFFFFFFFFFFFFFFFULL, 0x0ULL));
// Test with sparse polynomials (few bits set)
TEST_CONSTEXPR(match_m256i(_mm256_clmulepi64_epi128(((__m256i){0x5ULL, 0x0ULL, 0x9ULL, 0x0ULL}), ((__m256i){0x3ULL, 0x0ULL, 0x7ULL, 0x0ULL}), 0x00), 0xfULL, 0x0ULL, 0x3fULL, 0x0ULL));
#ifdef __AVX512F__
__m512i test_mm512_clmulepi64_epi128(__m512i A, __m512i B) {
// AVX512: @llvm.x86.pclmulqdq.512
return _mm512_clmulepi64_epi128(A, B, 0);
}
// Test constexpr evaluation for _mm512_clmulepi64_epi128
// Each 128-bit lane is processed independently
// Basic test cases for all imm8 values (0x00, 0x01, 0x10, 0x11)
// imm8=0x00: lower 64 bits of both operands in each lane
TEST_CONSTEXPR(match_m512i(_mm512_clmulepi64_epi128(((__m512i){0x1ULL, 0x0ULL, 0x2ULL, 0x0ULL, 0x4ULL, 0x0ULL, 0x8ULL, 0x0ULL}), ((__m512i){0x3ULL, 0x0ULL, 0x5ULL, 0x0ULL, 0x7ULL, 0x0ULL, 0x9ULL, 0x0ULL}), 0x00), 0x3ULL, 0x0ULL, 0xaULL, 0x0ULL, 0x1cULL, 0x0ULL, 0x48ULL, 0x0ULL));
// imm8=0x01: upper 64 bits of first operand, lower 64 bits of second in each lane
TEST_CONSTEXPR(match_m512i(_mm512_clmulepi64_epi128(((__m512i){0x0ULL, 0x1ULL, 0x0ULL, 0x2ULL, 0x0ULL, 0x4ULL, 0x0ULL, 0x8ULL}), ((__m512i){0x3ULL, 0x0ULL, 0x5ULL, 0x0ULL, 0x7ULL, 0x0ULL, 0x9ULL, 0x0ULL}), 0x01), 0x3ULL, 0x0ULL, 0xaULL, 0x0ULL, 0x1cULL, 0x0ULL, 0x48ULL, 0x0ULL));
// imm8=0x10: lower 64 bits of first operand, upper 64 bits of second in each lane
TEST_CONSTEXPR(match_m512i(_mm512_clmulepi64_epi128(((__m512i){0x1ULL, 0x0ULL, 0x2ULL, 0x0ULL, 0x4ULL, 0x0ULL, 0x8ULL, 0x0ULL}), ((__m512i){0x0ULL, 0x3ULL, 0x0ULL, 0x5ULL, 0x0ULL, 0x7ULL, 0x0ULL, 0x9ULL}), 0x10), 0x3ULL, 0x0ULL, 0xaULL, 0x0ULL, 0x1cULL, 0x0ULL, 0x48ULL, 0x0ULL));
// imm8=0x11: upper 64 bits of both operands in each lane
TEST_CONSTEXPR(match_m512i(_mm512_clmulepi64_epi128(((__m512i){0x0ULL, 0x1ULL, 0x0ULL, 0x2ULL, 0x0ULL, 0x4ULL, 0x0ULL, 0x8ULL}), ((__m512i){0x0ULL, 0x3ULL, 0x0ULL, 0x5ULL, 0x0ULL, 0x7ULL, 0x0ULL, 0x9ULL}), 0x11), 0x3ULL, 0x0ULL, 0xaULL, 0x0ULL, 0x1cULL, 0x0ULL, 0x48ULL, 0x0ULL));
// Complex test cases with edge values and non-zero upper 64-bit results
// Test with high bit set (0x8000000000000000) - produces result with upper bits
TEST_CONSTEXPR(match_m512i(_mm512_clmulepi64_epi128(((__m512i){(long long)0x8000000000000000ULL, 0x0ULL, (long long)0x8000000000000000ULL, 0x0ULL, (long long)0x8000000000000000ULL, 0x0ULL, (long long)0x8000000000000000ULL, 0x0ULL}), ((__m512i){0x2ULL, 0x0ULL, 0x4ULL, 0x0ULL, 0x8ULL, 0x0ULL, 0x10ULL, 0x0ULL}), 0x00), 0x0ULL, 0x1ULL, 0x0ULL, 0x2ULL, 0x0ULL, 0x4ULL, 0x0ULL, 0x8ULL));
// Test with all bits set (0xFFFFFFFFFFFFFFFF) - maximum value
// Note: Complex test case with all 1s removed - using simpler edge cases instead
// Test with large values that cause carry propagation
TEST_CONSTEXPR(match_m512i(_mm512_clmulepi64_epi128(((__m512i){(long long)0x1000000000000000ULL, 0x0ULL, (long long)0x2000000000000000ULL, 0x0ULL, (long long)0x4000000000000000ULL, 0x0ULL, (long long)0x8000000000000000ULL, 0x0ULL}), ((__m512i){0x0ULL, 0x10ULL, 0x0ULL, 0x20ULL, 0x0ULL, 0x40ULL, 0x0ULL, 0x80ULL}), 0x10), 0x0ULL, 0x1ULL, 0x0ULL, 0x4ULL, 0x0ULL, 0x10ULL, 0x0ULL, 0x40ULL));
// Test with values that produce results in upper 64 bits
TEST_CONSTEXPR(match_m512i(_mm512_clmulepi64_epi128(((__m512i){0x0ULL, (long long)0x8000000000000001ULL, 0x0ULL, (long long)0x8000000000000001ULL, 0x0ULL, (long long)0x8000000000000001ULL, 0x0ULL, (long long)0x8000000000000001ULL}), ((__m512i){0x0ULL, (long long)0x8000000000000001ULL, 0x0ULL, (long long)0x8000000000000001ULL, 0x0ULL, (long long)0x8000000000000001ULL, 0x0ULL, (long long)0x8000000000000001ULL}), 0x11), 0x1ULL, 0x4000000000000000ULL, 0x1ULL, 0x4000000000000000ULL, 0x1ULL, 0x4000000000000000ULL, 0x1ULL, 0x4000000000000000ULL));
// Test with polynomial-like values (common in CRC/GCM) across all lanes
TEST_CONSTEXPR(match_m512i(_mm512_clmulepi64_epi128(((__m512i){0x1ULL, 0x0ULL, (long long)0xFFFFFFFFFFFFFFFFULL, 0x0ULL, 0x5ULL, 0x0ULL, 0x9ULL, 0x0ULL}), ((__m512i){(long long)0xFFFFFFFFFFFFFFFFULL, 0x0ULL, 0x1ULL, 0x0ULL, 0x3ULL, 0x0ULL, 0x7ULL, 0x0ULL}), 0x00), (long long)0xFFFFFFFFFFFFFFFFULL, 0x0ULL, (long long)0xFFFFFFFFFFFFFFFFULL, 0x0ULL, 0xfULL, 0x0ULL, 0x3fULL, 0x0ULL));
#endif