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[PowerPC] Add DFP conversion instructions definitions and MC tests

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Add td definitions and asm/disasm tests for the quantum conversion
instructions in ISA 3.1 section 5.6.5

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D154394
This commit is contained in:
Lei Huang
2023-07-04 11:18:30 -04:00
parent 926f3759ec
commit f20660701d
4 changed files with 134 additions and 1 deletions
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26
llvm/lib/Target/PowerPC/PPCInstrDFP.td
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@@ -89,6 +89,30 @@ defm DRINTNQ: Z23Form_FRTB5_R1_RMC2r<63, 227, (outs fpairrc:$FRT),
(ins u1imm:$R, fpairrc:$FRB, u2imm:$RMC),
"drintnq", "$R, $FRT, $FRB, $RMC", []>;
// 5.6.5 DFP Conversion Instructions
defm DCTDP: XForm_26r<59, 258, (outs f8rc:$RST), (ins f8rc:$RB),
"dctdp", "$RST, $RB", IIC_FPGeneral, []>;
defm DCTQPQ: XForm_26r<63, 258, (outs fpairrc:$RST), (ins f8rc:$RB),
"dctqpq", "$RST, $RB", IIC_FPGeneral, []>;
defm DRSP: XForm_26r<59, 770, (outs f8rc:$RST), (ins f8rc:$RB),
"drsp", "$RST, $RB", IIC_FPGeneral, []>;
defm DRDPQ: XForm_26r<63, 770, (outs fpairrc:$RST), (ins fpairrc:$RB),
"drdpq", "$RST, $RB", IIC_FPGeneral, []>;
defm DCFFIX: XForm_26r<59, 802, (outs f8rc:$RST), (ins f8rc:$RB),
"dcffix", "$RST, $RB", IIC_FPGeneral, []>;
defm DCFFIXQ: XForm_26r<63, 802, (outs fpairrc:$RST), (ins f8rc:$RB),
"dcffixq", "$RST, $RB", IIC_FPGeneral, []>;
defm DCTFIX: XForm_26r<59, 290, (outs f8rc:$RST), (ins f8rc:$RB),
"dctfix", "$RST, $RB", IIC_FPGeneral, []>;
defm DCTFIXQ: XForm_26r<63, 290, (outs f8rc:$RST), (ins fpairrc:$RB),
"dctfixq", "$RST, $RB", IIC_FPGeneral, []>;
let Predicates = [HasP10Vector] in {
def DCFFIXQQ: XForm_26<63, 994, (outs fpairrc:$RST), (ins vrrc:$RB),
"dcffixqq $RST, $RB", IIC_FPGeneral, []>;
let RA = 1 in
def DCTFIXQQ: XForm_base_r3xo<63, 994, (outs vrrc:$RST), (ins fpairrc:$RB),
"dctfixqq $RST, $RB", IIC_FPGeneral, []>;
} // HasP10Vector
} // mayRaiseFPException
} // hasNoSchedulingInfo

1
llvm/lib/Target/PowerPC/PPCInstrVSX.td
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@@ -129,6 +129,7 @@ def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">;
def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">;
def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">;
def NoP10Vector: Predicate<"!Subtarget->hasP10Vector()">;
def HasP10Vector: Predicate<"Subtarget->hasP10Vector()">;
def PPCldsplatAlign16 : PatFrag<(ops node:$ptr), (PPCldsplat node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getAlign() >= Align(16) &&

54
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
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@@ -119,3 +119,57 @@
# CHECK: drintnq. 0, 10, 6, 2
0xfd 0x40 0x35 0xc7
# CHECK: dctdp 8, 2
0xed 0x00 0x12 0x04
# CHECK: dctdp. 8, 2
0xed 0x00 0x12 0x05
# CHECK: dctqpq 8, 2
0xfd 0x00 0x12 0x04
# CHECK: dctqpq. 8, 2
0xfd 0x00 0x12 0x05
# CHECK: drsp 20, 8
0xee 0x80 0x46 0x04
# CHECK: drsp. 20, 8
0xee 0x80 0x46 0x05
# CHECK: drdpq 20, 8
0xfe 0x80 0x46 0x04
# CHECK: drdpq. 20, 8
0xfe 0x80 0x46 0x05
# CHECK: dcffix 12, 7
0xed 0x80 0x3e 0x44
# CHECK: dcffix. 12, 7
0xed 0x80 0x3e 0x45
# CHECK: dcffixq 12, 8
0xfd 0x80 0x46 0x44
# CHECK: dcffixq. 12, 8
0xfd 0x80 0x46 0x45
# CHECK : dcffixqq 18, 20
0xfe 0x40 0xa7 0xc4
# CHECK: dctfix 8, 4
0xed 0x00 0x22 0x44
# CHECK: dctfix. 8, 4
0xed 0x00 0x22 0x45
# CHECK: dctfixq 8, 4
0xfd 0x00 0x22 0x44
# CHECK: dctfixq. 8, 4
0xfd 0x00 0x22 0x45
# CHECK: dctfixqq 8, 10
0xfd 0x01 0x57 0xc4

54
llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
View File

@@ -122,3 +122,57 @@
# CHECK-LE: drintnq. 1, 10, 6, 2 # encoding: [0xc7,0x35,0x41,0xfd]
# CHECK-BE: drintnq. 1, 10, 6, 2 # encoding: [0xfd,0x41,0x35,0xc7]
drintnq. 1, 10, 6, 2
# CHECK-LE: dctdp 8, 2 # encoding: [0x04,0x12,0x00,0xed]
# CHECK-BE: dctdp 8, 2 # encoding: [0xed,0x00,0x12,0x04]
dctdp 8, 2
# CHECK-LE: dctdp. 8, 2 # encoding: [0x05,0x12,0x00,0xed]
# CHECK-BE: dctdp. 8, 2 # encoding: [0xed,0x00,0x12,0x05]
dctdp. 8, 2
# CHECK-LE: dctqpq 8, 2 # encoding: [0x04,0x12,0x00,0xfd]
# CHECK-BE: dctqpq 8, 2 # encoding: [0xfd,0x00,0x12,0x04]
dctqpq 8, 2
# CHECK-LE: dctqpq. 8, 2 # encoding: [0x05,0x12,0x00,0xfd]
# CHECK-BE: dctqpq. 8, 2 # encoding: [0xfd,0x00,0x12,0x05]
dctqpq. 8, 2
# CHECK-LE: drsp 20, 8 # encoding: [0x04,0x46,0x80,0xee]
# CHECK-BE: drsp 20, 8 # encoding: [0xee,0x80,0x46,0x04]
drsp 20, 8
# CHECK-LE: drsp. 20, 8 # encoding: [0x05,0x46,0x80,0xee]
# CHECK-BE: drsp. 20, 8 # encoding: [0xee,0x80,0x46,0x05]
drsp. 20, 8
# CHECK-LE: drdpq 20, 8 # encoding: [0x04,0x46,0x80,0xfe]
# CHECK-BE: drdpq 20, 8 # encoding: [0xfe,0x80,0x46,0x04]
drdpq 20, 8
# CHECK-LE: drdpq. 20, 8 # encoding: [0x05,0x46,0x80,0xfe]
# CHECK-BE: drdpq. 20, 8 # encoding: [0xfe,0x80,0x46,0x05]
drdpq. 20, 8
# CHECK-LE: dcffix 12, 7 # encoding: [0x44,0x3e,0x80,0xed]
# CHECK-BE: dcffix 12, 7 # encoding: [0xed,0x80,0x3e,0x44]
dcffix 12, 7
# CHECK-LE: dcffix. 12, 7 # encoding: [0x45,0x3e,0x80,0xed]
# CHECK-BE: dcffix. 12, 7 # encoding: [0xed,0x80,0x3e,0x45]
dcffix. 12, 7
# CHECK-LE: dcffixq 12, 8 # encoding: [0x44,0x46,0x80,0xfd]
# CHECK-BE: dcffixq 12, 8 # encoding: [0xfd,0x80,0x46,0x44]
dcffixq 12, 8
# CHECK-LE: dcffixq. 12, 8 # encoding: [0x45,0x46,0x80,0xfd]
# CHECK-BE: dcffixq. 12, 8 # encoding: [0xfd,0x80,0x46,0x45]
dcffixq. 12, 8
# CHECK-LE: dctfix 8, 4 # encoding: [0x44,0x22,0x00,0xed]
# CHECK-BE: dctfix 8, 4 # encoding: [0xed,0x00,0x22,0x44]
dctfix 8, 4
# CHECK-LE: dctfix. 8, 4 # encoding: [0x45,0x22,0x00,0xed]
# CHECK-BE: dctfix. 8, 4 # encoding: [0xed,0x00,0x22,0x45]
dctfix. 8, 4
# CHECK-LE: dctfixq 8, 4 # encoding: [0x44,0x22,0x00,0xfd]
# CHECK-BE: dctfixq 8, 4 # encoding: [0xfd,0x00,0x22,0x44]
dctfixq 8, 4
# CHECK-LE: dctfixq. 8, 4 # encoding: [0x45,0x22,0x00,0xfd]
# CHECK-BE: dctfixq. 8, 4 # encoding: [0xfd,0x00,0x22,0x45]
dctfixq. 8, 4
# CHECK-LE: dcffixqq 18, 20 # encoding: [0xc4,0xa7,0x40,0xfe]
# CHECK-BE: dcffixqq 18, 20 # encoding: [0xfe,0x40,0xa7,0xc4]
dcffixqq 18, 20
# CHECK-LE: dctfixqq 8, 10 # encoding: [0xc4,0x57,0x01,0xfd]
# CHECK-BE: dctfixqq 8, 10 # encoding: [0xfd,0x01,0x57,0xc4]
dctfixqq 8, 10