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[mips] Mark the lwupc instruction as MIPS64 R6 only
The "The MIPS64 Instruction Set Reference Manual" [1] states that the `lwupc` is MIPS64 Release 6 only. It should not be supported for 32-bit CPUs. [1] https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf llvm-svn: 363886
This commit is contained in:
Simon Atanasyan
@@ -149,7 +149,6 @@ class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
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class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
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class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
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class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
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class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
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class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
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@@ -325,7 +324,6 @@ class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2,
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II_ADDIUPC>;
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class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>;
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class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>;
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class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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Operand ImmOpnd, InstrItinClass itin>
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@@ -926,7 +924,6 @@ let AdditionalPredicates = [NotInMicroMips] in {
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}
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def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def LWUPC : R6MMR6Rel, LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
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def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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@@ -36,6 +36,7 @@ class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011101>;
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class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
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class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b011101>;
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class LDPC_ENC : PCREL18_FM<OPCODE3_LDPC>;
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class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
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class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
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class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
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class CRC32D_ENC : SPECIAL3_2R_SZ_CRC<3,0>;
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@@ -72,6 +73,7 @@ class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
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class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
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class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
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class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
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class LWUPC_DESC : PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>;
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class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simmptr, II_LLD>;
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class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
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class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
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@@ -147,6 +149,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
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}
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def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
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def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS64R6;
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def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
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let DecoderNamespace = "Mips32r6_64r6_GP64" in {
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def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
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@@ -100,7 +100,6 @@
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0x04 0x00 0x60 0x41 # CHECK: evp $zero
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0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 4
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0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268
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0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268
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0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
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0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
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0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
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@@ -192,7 +192,6 @@
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0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20
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0xe8 0x37 0x96 0xb8 # CHECK: balc 14572260
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0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
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0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
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0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
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0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
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0xec 0x80 0x00 0x19 # CHECK: lapc $4, 100
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@@ -5,6 +5,7 @@
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# RUN: FileCheck %s < %t1
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.set noat
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lwupc $2,268 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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@@ -40,9 +40,6 @@
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# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A]
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# CHECK-FIXUP: # fixup A - offset: 0,
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# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
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# CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A]
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# CHECK-FIXUP: # fixup A - offset: 0,
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# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
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#------------------------------------------------------------------------------
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# Check that the appropriate relocations were created.
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#------------------------------------------------------------------------------
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@@ -58,7 +55,6 @@
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# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0
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# CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0
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# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0
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# CHECK-ELF: 0x2C R_MIPS_PC19_S2 bar 0x0
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# CHECK-ELF: ]
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addiupc $2,bar
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@@ -72,4 +68,3 @@
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addiu $2, $2, %pcrel_lo(bar)
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lapc $2,bar
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lwpc $2,bar
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lwupc $2,bar
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@@ -126,7 +126,6 @@ a:
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lapc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
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lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
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lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43]
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lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]
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mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
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mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
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modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb]
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