Commit Graph

560689 Commits

Author SHA1 Message Date
daniilavdeev
5f777b2c8f [dwarf] make dwarf fission compatible with RISCV relaxations 1/2 (#166597)
Currently, -gsplit-dwarf and -mrelax are incompatible options in Clang.
The issue is that .dwo files should not contain any relocations, as they
are not processed by the linker. However, relaxable code emits
relocations in DWARF for debug ranges that reside in the .dwo file when
DWARF fission is enabled.

This patch makes DWARF fission compatible with RISC-V relaxations. It
uses the StartxEndx DWARF forms in .debug_rnglists.dwo, which allow
referencing addresses from .debug_addr instead of using absolute
addresses. This approach eliminates relocations from .dwo files.
2025-11-26 00:52:22 +03:00
Razvan Lupusoru
4f39a4ff0a [acc][flang] Add getInitRegion() to GlobalVariableOpInterface (#169569)
Some globals (e.g., fir.global) have initialization regions that may
transitively reference other globals or type descriptors. Add
getInitRegion() to GlobalVariableOpInterface to retrieve these regions,
returning Region* (nullptr if the global uses attributes for
initialization, as with memref.global).
2025-11-25 13:44:11 -08:00
Haowei
49828c23b5 [Fuchsia] Bump minimal OS X target to 11.0 (#169568)
libcxx requires minimal macOS 11 to build. This patch bumps the minimal
OS X target in Fuchsia's cmake cache file to 11.0 to satisfy this
requirement.
2025-11-25 13:40:53 -08:00
Md Abdullah Shahneous Bari
9bf78ab8dd Revert "[GPUToXeVMPipeline][Pipeline] Modify pipeline to add convert-vector-to-llvm." (#169570)
Reverts llvm/llvm-project#166204

There was a build issue due to a missing dependency.
2025-11-25 15:36:54 -06:00
Florian Hahn
e894654532 [SCEV] Add tests for UDiv canonicalization of AddRecs that may wrap.
Add test cases for canonicalizing AddRecs that may wrap.
2025-11-25 21:33:26 +00:00
Christopher Ferris
074d17e9c8 [scudo] Lock/unlock MutexTSDs in disable/enable. (#169440)
It is possible that a fork could occur while MutexTSDs is being held and
then cause a deadlock in a forked process when something attempts to
lock it again. Instead add it to the enable/disable list of mutexes.
2025-11-25 13:20:09 -08:00
Alexey Bataev
00ffc70ba1 [SLP][NFC]Add a test with commutative instruction with non-commutative op, NFC 2025-11-25 12:58:20 -08:00
Florian Hahn
091aece72b [VPlan] Remove redundant transferFlags call from replicateByVF (NFC).
Flags are now passed on construction/cloning. Remove unnecessary
transferFlags call, and make code independent of VPRecipeWithIRFlags, to
support additional recipes in the future.
2025-11-25 20:57:42 +00:00
Helena Kotas
c475f8e5d8 [HLSL] Update vector swizzle elements individually (#169090)
When individual elements of a vector are updated via vector swizzle, it needs to be handled as separate store operations to the individual vector elements.

Clang treats vectors as one unit, so if a part of a vector needs to be updated, the whole vector is loaded, some elements modified, and then the whole vector is stored.

In HLSL vector elements are handled separately. We need to avoid this load/modify/store sequence to prevent overwriting other vector elements that might be getting updated in parallel.

Fixes #152815
2025-11-25 12:50:25 -08:00
Andy Kaylor
1c9368e01e [CIR] Upstream non-record array init handling (#169429)
This upstreams the code to handle member initialization for non-record
arrays.
2025-11-25 12:33:18 -08:00
Jay Foad
dbcf5688cc [AMDGPU] Simplify VT comparisons. NFC. (#169526)
Automated with `sed -i 's/\.Value//g' lib/Target/AMDGPU/*.td` plus a
tiny bit of manual reformatting.
2025-11-25 20:22:56 +00:00
Sam Elliott
8d920725ca [RISCV] Use FMV.D for moving GPRPairs on RV32_Zdinx (#169556)
This is noted by the specification, and should save a dynamic
instruction.

Code size should be no worse than before, as the pairs of moves can
usually be turned into two 16-bit moves, but `fmv.d` is always a 32-bit
instruction.

LLVM can look through a `FSGNJ_D_IN32X`, in
`RISCVInstrInfo::isCopyInstrImpl` which helps copy propagation.
2025-11-25 20:03:56 +00:00
Petr Penzin
ad3d9fb3ca [RISCV] tt-ascalon-d8 vector scheduling (#167066)
Add the vector scheduling model for tt-ascalon-d8 and corresponding
llvm-mca tests.

---------

Co-authored-by: Craig Topper <craig.topper@sifive.com>
2025-11-25 11:44:52 -08:00
Valentin Clement (バレンタイン クレメン)
0f941f6866 [flang][cuda] Add support to allocate scalar character types (#169550)
Add support for character declared like: 

```
subroutine sub1()
  character*4, device :: b
end subroutine
```
2025-11-25 11:41:35 -08:00
Sergei Druzhkov
3694798210 [lldb-dap] Add format support for evaluate request (#169132)
This patch adds support for format option in the `evaluate` request
according to
[DAP](https://microsoft.github.io/debug-adapter-protocol/specification#Requests_Evaluate)
specification. Also, fixed typo in `LLDB_DAP_INVALID_VARRERF` constant.
2025-11-25 22:38:25 +03:00
Krzysztof Drewniak
af0fcf85c8 [mlir][tblgen] Don't echo absolute paths into rewrite pattern source (#168984)
Currently, the declarative pattern rewrite generator will always print
the [source]:[line](s) from which a pattern came. This is a useful
debugging hint, but it causes problem when absolute paths are used as
arguments to mlir-tblgen (which LLVM's build rules automatically do).
Specifially, it causes the source to be tied to the build location,
harning reproducability and our collective ability to get ccache hits
from, say, separate worktrees.

This commit resolves the issue by replacing absolute paths in thes
"Generated from:" comments with their filenames. (The alternative would
have been to implement an entire file-prefix-map the way the C compilers
do, but since this is an isolated incident, I chose to resolve it
locally.)
2025-11-25 11:30:43 -08:00
Kazu Hirata
0917a38c69 [PowerPC] Fix a warning
This patch fixes:

  llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15676:17: error: unused
  variable 'CC' [-Werror,-Wunused-variable]
2025-11-25 11:22:31 -08:00
Maksim Panchenko
6c48fbc1dc [BOLT][Tests] Use AT&T assembler syntax only for X86 tests (#169541)
Enabling AT&T syntax for all tests is broken when X86 target is not
enabled as reported in #167225.
2025-11-25 11:15:24 -08:00
Krzysztof Parzyszek
ebe4006654 [mlir] Fix build failure with BUILD_SHARED_LIBS=ON
/usr/bin/ld: tools/mlir/lib/Dialect/GPU/Pipelines/CMakeFiles/obj.MLIRGP
UPipelines.dir/GPUToXeVMPipeline.cpp.o: in function `mlir::gpu::buildLo
werToXeVMPassPipeline(mlir::OpPassManager&, mlir::gpu::GPUToXeVMPipelin
eOptions const&)':
GPUToXeVMPipeline.cpp:(.text._ZN4mlir3gpu28buildLowerToXeVMPassPipeline
ERNS_13OpPassManagerERKNS0_24GPUToXeVMPipelineOptionsE+0x1293): undefin
ed reference to `mlir::createConvertVectorToLLVMPass()'
2025-11-25 13:05:14 -06:00
Craig Topper
eab23e199a [RISCV] Don't add Zilsd pairing hints if other part of the pair is reserved. (#169538) 2025-11-25 10:58:45 -08:00
Craig Topper
3a27fc4811 [RISCV] Omit VTYPE in VSETVLIInfo::print() when state is uninit or unknown. (#169459) 2025-11-25 10:57:17 -08:00
Matt Arsenault
2ee12f191a AMDGPU: Use RegClassByHwMode to manage GWS operand special case (#169373)
On targets that require even aligned 64-bit VGPRs, GWS operands
require even alignment of a 32-bit operand. Previously we had a hacky
post-processing which added an implicit operand to try to manage
the constraint. This would require special casing in other passes
to avoid breaking the operand constraint. This moves the handling
into the instruction definition, so other passes no longer need
to consider this edge case. MC still does need to special case this,
to print/parse as a 32-bit register. This also still ends up net
less work than introducing even aligned 32-bit register classes.

This also should be applied to the image special case.
2025-11-25 18:55:34 +00:00
Jez Ng
20ca85b69f [lld] macho: Support section branch relocations, including the 1-byte form (#169062)
I noticed that we had a hardcoded value of 4 for the pcrel section
relocations, which seems like an issue given that we recently added
support for 1-byte branch relocations in
https://github.com/llvm/llvm-project/pull/164439. The code included an
assert that the relevant relocation had the BYTE4 attribute, but that is
actually not enough to use a hardcoded value of 4: we need to assert
that the *other* `BYTE<n>` attributes are not set either.

However, since we did not support local branch relocations, that doesn't
seem to have mattered in practice. That said, local branch relocations
can be emitted by compilers, and ld64 does handle the 4-byte version of
them, so I've added support for it here.

ld64 actually seems to reject 1-byte section relocations, so the
questionable code is actually probably fine (minus the incorrect
assert). So we have two options: add an equivalent check in LLD, or just
support 1-byte local branch relocations. Supporting it actually requires
less code, so I've gone with that option here.
2025-11-25 13:54:46 -05:00
Matt Arsenault
622dbb372b AMDGPU: Add more tests for 32-bit constant address space (#168976)
The sub-dword cases just assert now, so comment those out.
2025-11-25 18:53:28 +00:00
Zahira Ammarguellat
2d78b1409e [OpenMP][Clang] Parsing/Sema support for need_device_ptr(fb_nullify/fb_preserve). (#168905)
This patch adds parsing, semantic handling, and diagnostics for the
`OpenMP 6.1 fb_nullify` and` fb_preserve` fallback modifiers used with
the `need_device_ptr` map modifier.
2025-11-25 13:48:37 -05:00
Amr Hesham
a8e0afe988 [CIR] ArraySubscriptExpr on ExtVectorElementExpr (#169158)
Implement ArraySubscriptExpr support for ExtVectorElementExpr
2025-11-25 19:44:13 +01:00
Erich Keane
dce95b2ea4 [OpenACC][CIR][NFC] Remove 'NYI' diagnostics, since we're done with t… (#169543)
…hese

We've finished all of the clauses/etc that we're going to use this
visitor for, so we can remove the SourceLocation we used just for that,
and replace all NYI with unreachables.
2025-11-25 18:43:15 +00:00
Walter Lee
6c8ff4f2bb [NVPTX] Fix maybe unused variable in 17852ded (#169542) 2025-11-25 18:35:15 +00:00
Drew Kersnar
8f1bb92bbf [NVPTX] Fix lit test issues from masked load/store implementation (#169535)
From this commit:
17852deda7,
Build was broken here:
https://lab.llvm.org/buildbot/#/builders/155/builds/15135/steps/7/logs/stdio.
I think this should fix things.
2025-11-25 12:27:31 -06:00
Matt Arsenault
1d30ae6e40 AMDGPU: Stop forcing RequiresCodeGenSCCOrder (#169522)
This hasn't been strictly necessary since c897c13dde.
Practically this makes little difference; we still enable IPRA
by default which implies this option. By removing this explicit
force, -enable-ipra=0 has the expected change in the pass pipeline
to remove the DummyCGSCC runs.
2025-11-25 13:23:55 -05:00
Ellis Hoag
d7dcc108fc [GitHub] Add review instructions for commit access requests (#168971)
As discussed in
https://discourse.llvm.org/t/clarification-on-how-to-accept-commit-access-requests/88728,
clarify reviewer instructions for how to accept commit access requests.
2025-11-25 10:22:23 -08:00
zhijian lin
0c9c62adf1 [PowerPC ]convert (setcc (and X, 1), 0, eq) to XORI (and X, 1), 1 (#168384)
Convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1`  , it will save one instruction.
2025-11-25 13:16:39 -05:00
David Stone
f545c2cec1 [clang][NFC] Don't copy into a vector just to iterate in IsInitListMemberExprInitialized (#169385) 2025-11-25 11:15:39 -07:00
Utkarsh Saxena
4822f4986f [LifetimeSafety] Add parameter lifetime tracking in CFG (#169320)
This PR enhances the CFG builder to properly handle function parameters
in lifetime analysis:

1. Added code to include parameters in the initial scope during CFG
construction for both `FunctionDecl` and `BlockDecl` types
2. Added a special case to skip reference parameters, as they don't need
automatic destruction
3. Fixed several test cases that were previously marked as "FIXME" due
to missing parameter lifetime tracking

Previously, Clang's lifetime analysis was not properly tracking the
lifetime of function parameters, causing it to miss important
use-after-return bugs when parameter values were returned by reference
or address. This change ensures that parameters are properly tracked in
the CFG, allowing the analyzer to correctly identify when stack memory
associated with parameters is returned.

Fixes https://github.com/llvm/llvm-project/issues/169014
2025-11-25 18:06:42 +00:00
Md Abdullah Shahneous Bari
d5aa686636 [GPUToXeVMPipeline][Pipeline] Modify pipeline to add convert-vector-to-llvm. (#166204)
`convert-vector-to-llvm` pass applies a set of vector transformation
patterns that are not included in the standard `convert-to-llvm` pass
interface. These additional transformations are required to properly
lower MLIR vector operations. Since not all vector ops have direct
`llvm` dialect lowering, many of them must first be progressively
rewritten into simpler or more canonical vector ops, which are then
lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is
necessary to ensure a complete and correct lowering of vector operations
to the `llvm` dialect.
2025-11-25 12:03:29 -06:00
Razvan Lupusoru
6a6b99aa80 [acc][flang][cir] Add recipes to data entry operations (#149210)
This patch refactors the OpenACC dialect to attach recipe symbols
directly to data operations (acc.private, acc.firstprivate,
acc.reduction)
rather than to compute constructs (acc.parallel, acc.serial, acc.loop).

Motivation:
The previous design required compute constructs to carry both the recipe
symbol and the variable reference, leading to complexity. Additionally,
recipes were required even when they could be generated automatically
through MappableType interfaces.

Changes:
- Data operations (acc.private, acc.firstprivate, acc.reduction) now
  require a 'recipe' attribute referencing their respective recipe
  operations
- Verifier enforces recipe attribute presence for non-MappableType
  operands; MappableType operands can generate recipes on demand
- Compute constructs (acc.parallel, acc.serial, acc.loop) no longer
  carry recipe symbols in their operands
- Updated flang lowering to attach recipes to data operations instead
  of passing them to compute constructs

Format Migration:
Old format:
```
  acc.parallel private(@recipe -> %var : !fir.ref<i32>) { ... }
```

New format:
```
  %private = acc.private varPtr(%var : !fir.ref<i32>)
              recipe(@recipe) -> !fir.ref<i32>
  acc.parallel private(%private : !fir.ref<i32>) { ... }
```

Test Updates:
- Updated all CIR and Flang OpenACC tests to new format
- Fixed CHECK lines to verify recipe attributes on data operations
2025-11-25 17:59:45 +00:00
Min-Yih Hsu
44cffbe5d8 [RISCV] Propagate SDNode flags when combining (fmul (fneg X), ...) (#169460)
In #157388, we turned `(fmul (fneg X), Y)` into `(fneg (fmul X, Y))`.
However, we forgot to propagate SDNode flags, specifically fast math
flags, from the original FMUL to the new one. This hinders some of the
subsequent (FMA) DAG combiner patterns that relied on the contraction
flag and as a consequence, missed some of the opportunities to generate
negation FMA instructions like `fnmadd`.

This patch fixes this issue by propagating the flags.

---------

Co-authored-by: Craig Topper <craig.topper@sifive.com>
2025-11-25 17:53:57 +00:00
Matt Arsenault
84df446af9 AMDGPU: Remove DummyCGSCC use after buffer lowering passes (#169519)
The fixme the comment refers to was removed.
2025-11-25 12:53:13 -05:00
Valeriy Savchenko
d125cab13f [InstCombine] Support multi-use values in cast elimination transforms (#165877)
`canEvaluateTruncated` and `canEvaluateSExtd` previously rejected
multi-use values to avoid duplication. This was overly conservative, if
all users of a multi-use value are part of the transform, we can
evaluate it in a different type without duplication.

This change tracks visited values and defers decisions on multi-use
values until we verify all their users were visited.
`EvaluateInDifferentType` now memoizes multi-use values to avoid
creating duplicates.

Applied to truncation and sext. Zext unchanged due to its dual-return
nature.
2025-11-25 17:43:26 +00:00
Kaitlin Peng
4877c593a8 [SPIRV] Add PreLegalizer pattern matching for faceforward (#139959)
Tasks completed:
- Pattern match`select(fcmp(dot(p2, p3), 0), p1, -p1)` to
`faceforward(p1, p2, p3)`
- Add pattern matching tests to
`prelegalizercombiner-select-to-faceforward.mir` and `faceforward.ll`
- Add CL extension error test
`llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll`
- Add CL extension test for no pattern matching in
`llvm/test/CodeGen/SPIRV/opencl/faceforward.ll`

Closes #137255.
2025-11-25 09:41:35 -08:00
Benjamin Chetioui
012721d320 [mlir][python] Propagate error diagnostics when an op couldn't be created. (#169499) 2025-11-25 17:41:01 +00:00
Keith Smiley
83d9c636b7 [bazel] Add alias for zlib-ng for WORKSPACE compat (#169530)
The consumer of zlib in third-party/BUILD.bazel expects zlib-ng from the
BCR, if you still load this version from your WORKSPACE / MODULE.bazel
you need to use this name instead.
2025-11-25 09:38:01 -08:00
Gergely Bálint
4533699245 [BOLT][BTI] Add MCPlusBuilder::isBTILandingPad (#167306)
- takes both implicit and explicit BTIs into account
- fix related comment in 
   llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
2025-11-25 18:37:30 +01:00
Andy Kaylor
1441f04585 [CIR] Upstream reserved placement new handling (#169436)
This upstreams the code to support reserved placement new calls.
2025-11-25 09:33:27 -08:00
Joel E. Denny
8380a48aa0 [PGO] Add REQUIRES to test (#169531)
The test was added by b8ef25aa64. It
failed on at least the following bots, but the failure did not reproduce
on my test machines or in pre-commit CI:

- https://lab.llvm.org/buildbot/#/builders/190/builds/31643
- https://lab.llvm.org/buildbot/#/builders/65/builds/25949
- https://lab.llvm.org/buildbot/#/builders/154/builds/24417

d69e701496 did not fix the failure.
Hopefully this will.
2025-11-25 12:33:04 -05:00
Erich Keane
53e5cfdf8b [OpenACC][CIR] link clause lowering for global declare (#169524)
The 'link' clause is like the rest of the global clauses (copyin,
    create, device_resident), except it only has an entry op(thus no
dtor).

This patch also removes a bunch of now stales TODOs from the tests.
2025-11-25 17:23:50 +00:00
Manuel Carrasco
a860c8378f Revert "[clang][Driver] Support for the SPIR-V backend when compiling HIP (#167543)" (#169528)
This reverts commit 1a036732d2.

Reverted due to a failure in hip-spirv-backend-opt.c for
fuchsia-x86_64-linux.
2025-11-25 17:23:30 +00:00
Matt Arsenault
5017370a1c AMDGPU: Add baseline test for gws handling with AGPR inputs (#169372) 2025-11-25 12:04:09 -05:00
Matt Arsenault
1c5b1501ca CodeGen: Move libcall lowering configuration to subtarget (#168621)
Previously libcall lowering decisions were made directly
in the TargetLowering constructor. Pull these into the subtarget
to facilitate turning LibcallLoweringInfo into a separate analysis
in the future.
2025-11-25 11:59:56 -05:00
Hristo Hristov
5999cc8cee [libc++][stack] Applied [[nodiscard]] (#169468)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.

-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
2025-11-25 18:55:34 +02:00