Commit Graph

11005 Commits

Author SHA1 Message Date
Kazu Hirata
cbde2124f1 Use APInt::popcount instead of APInt::countPopulation (NFC)
This is for consistency with the C++20-style bit manipulation
functions in <bit>.
2023-02-19 11:29:12 -08:00
Fabian
09fd9ef4f4 [mlir] Execute all requested translations in MlirTranslateMain
Currently, MlirTranslateMain only executes one of the requested translations, and does not error if multiple are specified. This commit enables translations to be chained in the specified order.

This makes round-trip tests easier, since existing import/export passes can be reused and no combined round-trip passes have to be registered (example: mlir-translate  -serialize-spirv -deserialize-spirv).

Additionally, by leveraging TranslateRegistration with file-to-file TranslateFunctions, generic pre- and post-processing can be added before/after conversion to/from MLIR.

Reviewed By: lattner, Mogball

Differential Revision: https://reviews.llvm.org/D143719
2023-02-18 21:31:59 +01:00
Hanhan Wang
5fa9933c13 [mlir][tensor] Do not use affine ops on non-perfect-tiling unpack cases.
Do not create an Affine ops for expanded size because the affine op is
too complicated which would hit an assertion in affine ops
simplification.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D144151
2023-02-17 11:08:03 -08:00
Jeff Niu
f25cfd339a [mlir] Reintroduce API for creating operations with a DictionaryAttr
This patch reintroduces an API to create operations with a pre-existing
DictionaryAttr. This API does not populate the attributes with any
default attributes the operation may have, like the API that takes a
NamedAttrList does. NamedAttrList is effective at not re-hashing the
attributes if no default attributes were added, but this new API speeds
up clone-heavy workloads slightly (~5%).

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D144204
2023-02-17 10:07:53 -08:00
Thomas Raoux
ddeb55ab33 [mlir] add option to multi-buffering
Allow user to apply multi-buffering transformation for cases where proving
that there is no loop carried dependency is not trivial. In this case user needs
to ensure that the data are written and read in the same iteration otherwise the
result is incorrect.

Differential Revision: https://reviews.llvm.org/D144227
2023-02-17 15:34:51 +00:00
Christian Ulmann
87a0479538 [mlir][llvm] Fuse access_group & loop export (NFC)
This commit moves the access group translation into the
LoopAnnotationTranslation class as these two metadata kinds only appear
together.

Drops the access group cleanup from `ModuleTranslation::forgetMapping`
as this is only used on function regions. Access groups only appear in the
region of a global metadata operation and will thus not be cleaned here.

Analogous to https://reviews.llvm.org/D143577

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D144253
2023-02-17 15:31:21 +01:00
Christian Ulmann
e133cb9c6d [mlir][llvm] Add DINamespace attribute
This commit introduces the DINamespaceAttr to model LLVM's DINamespace metadata.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D144243
2023-02-17 13:09:29 +01:00
Alexander Belyaev
cdf8f06469 [mlir] Add a folder for lbs, ubs, steps of scf.forall.
Differential Revision: https://reviews.llvm.org/D144245
2023-02-17 11:01:13 +01:00
Christian Ulmann
bf91cd6ea9 [mlir][llvm] Verify LLVM module before import
This commit ensures that the importing of LLVM modules first verifies
that the module is even valid. As many tests did not work with valid
LLVM IR, they were fixed as part of this commit.

Some error messages were only reachable with invalid input IR, thus they
were replaced with a failures.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D144186
2023-02-17 10:25:23 +01:00
Alexander Belyaev
eb2f946e78 [mlir][scf] Rename ForeachThreadOp->ForallOp, PerformConcurrentlyOp->InParallelOp.
Differential Revision: https://reviews.llvm.org/D144242
2023-02-17 09:59:39 +01:00
Tobias Gysi
6f4af64b74 [mlir][llvm] Add atomic support to the LoadOp.
This revision adds atomic support to the LoadOp. It chooses
to print the atomic keywords together with the syncscope and
ordering arguments, which simplifies parsing and printing compared
to the LLVM IR printer that puts the atomic keyword at the beginning.
It uses the ordering attribute to check if the load is atomic.

The revision also implements verifiers to ensure the constraints
that apply to atomic load operations are checked.

Reviewed By: Dinistro

Differential Revision: https://reviews.llvm.org/D144112
2023-02-17 09:29:40 +01:00
Johannes de Fine Licht
a048d7394b [MLIR][LLVM] Only disallow inlining for selected function attributes.
This loosens the requirement of no passthrough function attribute being
present to checking for specific attributes that prevent inlining. Since
these attributes are no longer strictly passthrough, they should
eventually be upgraded to some form of addressable attributes.

Drops the expensive StringSwitches over call and function attributes in
favor of selectively disallowing attributes that prevent inlining
(similiar to the LLVM inliner), thereby moving to a less conservative
approach.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D144104
2023-02-17 09:18:17 +01:00
Alexander Belyaev
310deca248 [mlir] Add loop bounds to scf.foreach_thread.
https://discourse.llvm.org/t/rfc-parallel-loops-on-tensors-in-mlir/68332

Differential Revision: https://reviews.llvm.org/D144072
2023-02-17 08:57:52 +01:00
Thomas Raoux
0eabb884ab [mlir][gpu] NFC let user pick the threadID values when distributing foreach_thread
Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D144219
2023-02-17 03:25:15 +00:00
Thomas Raoux
e3a88a41af Revert "[mlir][vector] Prevent duplicating operations during vector distribute"
This reverts commit 2fc3c5c34c.
2023-02-17 03:07:16 +00:00
Kiran Chandramohan
22cdeb54a1 [MLIR][OpenMP] Add Conversion for Atomic Update Op
Reviewed By: TIFitis

Differential Revision: https://reviews.llvm.org/D143964
2023-02-16 23:57:35 +00:00
Peiming Liu
9e8d9316ce [mlir][sparse] allow foreach operation to generate out-of-order loop on non-annotated tensor.
No need for a temp COO and sort even when converting dense -> CSC, we can instead rotate the loop to yield a ordered coordinates at beginning.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D144213
2023-02-16 23:23:20 +00:00
bixia1
c2e248c6ae [mlir][sparse] Remove the expansion of symmetric MTX in the sparse tensor storage.
We will support symmetric MTX without expanding the data in the sparse tensor
storage.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D144059
2023-02-16 13:02:17 -08:00
Nicolas Vasilache
ec640382fc [mlir][MemRef] NFC - Add debug information to MultiBuffer.cpp 2023-02-16 07:19:58 -08:00
Matthias Springer
e44f405bb4 [mlir][bufferization] Fix bug in findValueInReverseUseDefChain
`alwaysIncludeLeaves` was not respected by all code paths.

Differential Revision: https://reviews.llvm.org/D144187
2023-02-16 16:12:31 +01:00
Maya Amrami
ace6072bca [mlir] PromoteBuffersToStackPass - Copy attributes of original AllocOp
Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D143185
2023-02-16 17:06:45 +02:00
Christian Ulmann
28542e99bb [mlir][llvm] Use before def debug intrinsic import
This commit adds special handling for the debug intrinsic value
handling. LLVM allows to relax the def before use property for debug
intrinsics, so this property cannot be assumed for metadata values.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D144177
2023-02-16 15:49:23 +01:00
Nicolas Vasilache
96179dff46 [mlir][Linalg] Add a transform dialect op to rewrite ops to destination passing style.
A new transform dialect op is introduced to perform the rewrite.
The test pass option is now obsolete and is removed in favor of the transform.

In the process I realized the tensor.pad nofold attribute was not taken into account
and added support to emit a bufferization.alloc_tensor + linalg.copy.

Reviewed By: springerm

Differential Revision: https://reviews.llvm.org/D143943
2023-02-16 05:26:33 -08:00
Johannes Reifferscheid
b58daf91d6 Add a lowering for memref.dealloc with unranked memrefs.
This is permitted by the op, but the current lowering generates invalid IR.

Reviewed By: springerm

Differential Revision: https://reviews.llvm.org/D144090
2023-02-16 14:19:16 +01:00
Christian Ulmann
873ea45115 [mlir][llvm] Rename void debug type to null
This commit renames the "di_void_result_type" to "di_null_type" as LLVM
does use null not exclusively for void types. An added test demonstrates
this for variadic function declarations, whose DISubroutine indicates the
start of variadic types with `null`.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D144109
2023-02-16 12:13:24 +01:00
Quentin Colombet
4bc2357c3d [mlir][MemRef|Tensor] Fix the handling of DimOp
Although specifying an index that is out of bounds for both `memref.dim`
and `tensor.dim` produces an undefined behavior, this is still valid IR.
In particular, we could expose an out of bound index because of some
optimizations, for instance as demonstrated with
https://github.com/llvm/llvm-project/issues/60295, and this shouldn't
cause the compiler to abort.

This patch removes the overzealous verifier checks and properly handles
out of bound indices (as in it doesn't crash the compiler, but still
produces UB).

This fixes https://github.com/llvm/llvm-project/issues/60295.

Note: That `shape.dim` has a similar problem but we're not supposed to
produce UB in this case. Instead we're supposed to propagate an error in
the resulting value and I don't know how to do that at the moment. Hence I
left this part out of the patch.

Differential Revision: https://reviews.llvm.org/D143999
2023-02-16 11:38:19 +01:00
Tobias Gysi
4469ec1d19 [mlir][llvm] Import alias scope metadata from LLVM IR.
The revision adds support for importing alias.scope and noalias metadata
from LLVM IR into LLVM dialect. It also adds a verifier to the
AliasScopeMetadataOp to check that the associated domain exists
and is of type AliasScopeDomainMetadataOp.

Reviewed By: Dinistro

Differential Revision: https://reviews.llvm.org/D143923
2023-02-16 09:52:59 +01:00
jacquesguan
86c8ea9ac9 [mlir] Add check for value that might be null.
Because we are generating uninitialized value for no integer type and use `isUninitialized()` to judge if it is valid after https://reviews.llvm.org/rG93f081c896536112e1ca8133991d23cb1134793a, we should check the value before use `getValue` to get it.
Fixes https://github.com/llvm/llvm-project/issues/59984.

Reviewed By: Mogball

Differential Revision: https://reviews.llvm.org/D141661
2023-02-16 16:02:35 +08:00
Lei Zhang
a1aad28d29 [mlir][vector] NFC: Improve vector type accessor methods
Plain `getVectorType()` can be quite confusing and error-prone
given that, well, vector ops always work on vector types, and
it can commonly involve both source and result vectors. So this
commit makes various such accessor methods to be explicit w.r.t.
source or result vectors.

Reviewed By: ThomasRaoux

Differential Revision: https://reviews.llvm.org/D144159
2023-02-16 04:08:33 +00:00
Kazu Hirata
5382d28815 [mlir] Use std::optional instead of llvm::Optional (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2023-02-15 19:40:10 -08:00
Peiming Liu
c738b430c4 [mlir][sparse] introduce operations to query sparse tensor slice offset/strides at the given dimenion
Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D141442
2023-02-16 00:31:11 +00:00
Peiming Liu
e2e83f4c8f [mlir][sparse] support coiteration over sparse tensor slices
Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D140736
2023-02-15 23:52:22 +00:00
wren romano
ae7942e296 [mlir][sparse] adding SparseTensorType::get{Pointer,Index}Type methods
Depends On D143800

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D143946
2023-02-15 14:37:55 -08:00
wren romano
d950bdc73e [mlir][sparse] misc code cleanup
* Flattening/simplifying some nested conditionals
* const-ifying some local variables

Depends On D143800

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D143949
2023-02-15 13:29:00 -08:00
wren romano
bb4fc6b6d6 [mlir][sparse] Adding SparseTensorType::{operator==, hasSameDimToLvlMap}
Depends On D143800

Reviewed By: aartbik, Peiming

Differential Revision: https://reviews.llvm.org/D144052
2023-02-15 12:05:29 -08:00
Hanhan Wang
be75cf931f [mlir][tensor] Fix a bug in tiling unpack op.
The inner tiling sizes could be dynamic (which are Values). In this
context, they should be added to tiledOperand when cloning the op.

Reviewed By: chelini

Differential Revision: https://reviews.llvm.org/D143978
2023-02-15 10:25:50 -08:00
Lei Zhang
78e172fc92 [mlir][spirv] Support i32 memref.atomic_rmw conversion
These cases can be directly mapped to spirv.AtomicI* ops.

Reviewed By: kuhar

Differential Revision: https://reviews.llvm.org/D143952
2023-02-15 17:53:56 +00:00
Thomas Raoux
3cf7f22498 [mlir][vectorToGPU] Fix type used when folding transpose into read op
Pick the right result type when folding transpose op into a read

Differential Revision: https://reviews.llvm.org/D144113
2023-02-15 17:34:09 +00:00
Krzysztof Drewniak
22f0c7a451 [mlir][AMDGPU] 8-bit float usage in the AMDGPU dialect
Upcoming AMD hardware will include functions that accept 8-bit floats.
Specifically, there are MFMA instructions that accept 8-bit floats,
either using the same or mixed formats. This patch adds MLIR wrappers
for these intrinsics and explicitly adds support for 8-bit floats in
the gpu-to-rocdl conversion by way of amdgpu-to-rocdl.

Since LLVM does not have f8 types, when targeting LLVM for compilation
on an AMD GPU, both f8 types used on AMD hardware (f8E5M2FNUZ and
f8E4M3FNUZ) are rewritten to i8.

This patch also relaxes the restriction that the types of both source
operands to a amdgpu.mfma instructions match exactly, as this is not
necessarily required for the bf8 (f8E5M2FNUZ) and fp8 (f8E4M3FNUZ)
instructions. In addition, since the buffer_{load,store} operations
maintain a whitelist of permitted types, we add the relevant f8 types
to that list.

This patch does not add any implementations of arithmetic operations
for f8 types.

Reviewed By: jakeh-gc

Differential Revision: https://reviews.llvm.org/D143956
2023-02-15 16:46:08 +00:00
Matthias Springer
6dd9d18204 [mlir][linalg] Fix insertion point bug in D144022
This should have been part of D144022.
2023-02-15 16:54:23 +01:00
Matthias Springer
c645eb0d03 [mlir][memref] Bufferize memref.tensor_store op
This change adds the BufferizableOpInterface implementation for memref.tensor_store.

Differential Revision: https://reviews.llvm.org/D144080
2023-02-15 15:26:57 +01:00
Matthias Springer
01581e28ad [mlir][linalg] Add bufferize_to_allocation transform op
This transform materializes a buffer allocation for a given tensor value. All uses of the original value are replaced with the allocation.

Certain non-DPS ops may have an optimized lowering path that bufferizes the entire defining op. Such optimization is added for `tensor.pad` as part of this change.

The resulting IR can be further bufferized with One-Shot Bufferize.

Differential Revision: https://reviews.llvm.org/D144022
2023-02-15 15:22:46 +01:00
Matthias Springer
3ef062a4bd [mlir][transform] Add transform.get_result op
This transform op returns a value handle pointing to the specified OpResult of the targeted op.

Differential Revision: https://reviews.llvm.org/D144087
2023-02-15 14:16:50 +01:00
Matthias Springer
8f7e7400b7 [mlir][bufferization] Add restrict and writable attrs to to_tensor
`restrict` is similar to the C++ restrict keyword. Results of `to_tensor` that have the `restrict` attribute are guaranteed to not alias any other `to_tensor` result (after bufferization).

Note: Since `to_memref` ops are not supported by One-Shot Bufferize and all bufferizable ops follow DPS rules (i.e., the buffer of the result is the buffer of an operand or an alias thereof), the buffer of a `to_tensor` op that has the `restrict` attribute is always an entirely "new" buffer that is not aliasing with the future buffer of any tensor value in the entire program. This makes such `to_tensor` ops "safe" from a bufferization perspective; they cannot cause RaW conflicts.

Differential Revision: https://reviews.llvm.org/D144021
2023-02-15 10:04:54 +01:00
Andrzej Warzynski
71712440bb [mlir] Add vectorize_nd_extract attribute to the masked_vectorize Op
This patch simply adds `vectorize_nd_extract` (that's currently only
used for the `vectorize` Op) to `masked_vectorize`. A test is added to
verify that it works as expected - it prevents the masked vectorisation
of `tensor.extract`, which is currently not supported.

Differential Revision: https://reviews.llvm.org/D142634
2023-02-15 08:47:03 +00:00
Lorenzo Chelini
30d542f9b2 [MLIR][Tensor] Introduce a pattern to propagate through tensor.pad
Introduce a pattern to 'push down' a `tensor.unpack` through a
`tensor.pad`. The propagation happens if the unpack does not touch the
padded dimensions.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D143907
2023-02-15 08:48:55 +01:00
Ingo Müller
4bba8bd33e [mlir] Add RewriterBase::replaceAllUsesWith for Blocks.
When changing IR in a RewriterPattern, all changes must go through the
rewriter. There are several convenience functions in RewriterBase that
help with high-level modifications, such as replaceAllUsesWith for
Values, but there is currently none to do the same task for Blocks.

Reviewed By: mehdi_amini, ingomueller-net

Differential Revision: https://reviews.llvm.org/D142525
2023-02-15 07:23:21 +00:00
Mehdi Amini
72429a42ac Add a pass that builds a debug info scope for LLVMFuncOp (adding a DISubprogramAttr)
This may be seen as a hack, but it allows for any piece of MLIR to be able
to end up with DWARF debug info through LLVM.
Assuming the operations in the function have location such as FileLineCol,
this provides backtraces with line tables and allows to step in a debugger.
That makes this pass a perfect companion to -snapshot-op-locations

It was also the default behavior of MLIR to LLVM IR translation until MLIR
got support for proper debug info attributes.

Differential Revision: https://reviews.llvm.org/D144069
2023-02-14 22:43:26 -08:00
Diego Caballero
1427277eed [mlir][Vector] Enable masking for static shapes
Support for masking static shapes was already implemented in the past
but not enabled so this patch is just removing a pre-condition check and
adding some tests with static shapes.

Reviewed By: ThomasRaoux

Differential Revision: https://reviews.llvm.org/D143937
2023-02-15 06:10:22 +00:00
Diego Caballero
1ac874c9aa [mlir][Vector] Add support for masked vector gather ops
This patch adds support for masked vector.gather ops using the
vector.mask representation. It includes the implementation of the
MaskableOpInterface, Linalg vectorizer support and lowering to LLVM.

Reviewed By: ThomasRaoux

Differential Revision: https://reviews.llvm.org/D143939
2023-02-15 06:10:22 +00:00