Commit Graph

278448 Commits

Author SHA1 Message Date
John Baldwin
dfbbbdf8cd [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
This supports the soft-float ABI only and has been tested with both clang
and gcc on FreeBSD.

Reviewed By: sdardis, compnerd

Differential Revision: https://reviews.llvm.org/D38110

llvm-svn: 320528
2017-12-12 21:43:36 +00:00
Gheorghe-Teodor Bercea
b4c74c6603 [OpenMP] Add function attribute for triggering data sharing.
Summary:
The backend should only emit data sharing code for the cases where it is needed.
A new function attribute is used by Clang to enable data sharing only for the cases where OpenMP semantics require it and there are variables that need to be shared.

Reviewers: hfinkel, Hahnfeld, ABataev, carlo.bertolli, caomhin

Reviewed By: ABataev

Subscribers: cfe-commits, jholewinski

Differential Revision: https://reviews.llvm.org/D41123

llvm-svn: 320527
2017-12-12 21:38:43 +00:00
Rui Ueyama
338c4b2336 Use the standard error handling mechanism in MinGW driver.
Differential Revision: https://reviews.llvm.org/D41127

llvm-svn: 320526
2017-12-12 20:34:38 +00:00
Alexey Bataev
83c15b1363 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320525
2017-12-12 20:28:46 +00:00
Raoul Wols
212bcf8370 [clangd] (Attempt to) read clang-format file for document formatting
Summary:
Takes into account the clang-format file of the project, if any.
Reverts to LLVM if nothing is found. Replies with an error if any error occured.
For instance, a parse error in the clang-format YAML file.

Reviewers: ilya-biryukov, sammccall, Nebiroth, malaperle, krasimir

Reviewed By: sammccall

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D41031

llvm-svn: 320524
2017-12-12 20:25:06 +00:00
Krzysztof Parzyszek
edcd9dcbc4 [Hexagon] Better detection of identity and undef masks in shuffles
llvm-svn: 320523
2017-12-12 20:23:12 +00:00
Vedant Kumar
c8e1c0945a Add an #include to appease an older clang, NFC
Add in a missing #include that AppleClang-900 complains about when
building with -DLLVM_ENABLE_MODULES.

llvm-svn: 320522
2017-12-12 20:19:40 +00:00
Kelvin Li
1ce87c7051 [OpenMP] Diagnose function name on the link clause
This patch is to add diagnose when a function name is
specified on the link clause. According to the  OpenMP
spec, only the list items that exclude the function 
name are allowed on the link clause.

Differential Revision: https://reviews.llvm.org/D40968

llvm-svn: 320521
2017-12-12 20:08:12 +00:00
Rui Ueyama
1ce416c635 Remove trailing whitespace.
llvm-svn: 320520
2017-12-12 20:00:30 +00:00
Don Hinton
7dd474ab7b [cmake] Follow-up to rL320494.
EXISTS requires full paths.

llvm-svn: 320519
2017-12-12 19:47:40 +00:00
Martin Storsjo
71663a2eac [MinGW] Don't pass -dynamicbase:no by default for arm/arm64
The linker refuses using -dynamicbase:no on these architectures.

Stop passing -dynamicbase (which just reinforces the lld-link
default) for simplicity.

Differential Revision: https://reviews.llvm.org/D41052

llvm-svn: 320518
2017-12-12 19:39:18 +00:00
Martin Storsjo
6ea167cc43 [COFF] Disallow -dynamicbase:no for arm and arm64
This matches what MSVC link.exe does.

Differential Revision: https://reviews.llvm.org/D41051

llvm-svn: 320517
2017-12-12 19:39:13 +00:00
Krzysztof Parzyszek
40a605f1be [Hexagon] Fix wrong order of operands for vmux
Shuffle generation uses vmux to collapse vectors resulting from two
individual shuffles into one. The indexes of the elements selected
from the first operand were indicated by 0xFF in the constant vector
used in the compare instruction, but the compare (veqb) set the bits
corresponding to the 0x00 elements, thus inverting the selection.

Reverse the order of operands to vmux to get the correct output.

llvm-svn: 320516
2017-12-12 19:32:41 +00:00
Fiona Glaser
b8a330c42a Reassociate: add global reassociation algorithm
This algorithm (explained more in the source code) takes into account
global redundancies by building a "pair map" to find common subexprs.

The primary motivation of this is to handle situations like

foo = (a * b) * c
bar = (a * d) * c

where we currently don't identify that "a * c" is redundant.

Accordingly, it prioritizes the emission of a * c so that CSE
can remove the redundant calculation later.

Does not change the actual reassociation algorithm -- only the
order in which the reassociated operand chain is reconstructed.

Gives ~1.5% floating point math instruction count reduction on
a large offline suite of graphics shaders.

llvm-svn: 320515
2017-12-12 19:18:02 +00:00
Roman Lebedev
1b318b1016 [msan] LIT: Add lld testing config
Summary: A follow-up for D39508, with memory sanitizer changes.

Reviewers: eugenis, vitalybuka

Reviewed By: eugenis

Subscribers: mgorny, mehdi_amini, kcc, #sanitizers, llvm-commits

Tags: #sanitizers, #lld

Differential Revision: https://reviews.llvm.org/D40768

llvm-svn: 320514
2017-12-12 19:17:52 +00:00
Alexey Bataev
fa0a76dbcc Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320510 - again sanitizers bbots.

llvm-svn: 320513
2017-12-12 19:12:34 +00:00
Sanjoy Das
1074eb225b Reapply "[X86] Flag BroadWell scheduler model as complete"
This reverts commit r320508, in effect re-applying r320308.  Simon has already
reverted the parts that caused the crash that motivated the revert in r320492.

llvm-svn: 320512
2017-12-12 19:11:31 +00:00
Hiroshi Yamauchi
f3bda1daa2 Split IndirectBr critical edges before PGO gen/use passes.
Summary:
The PGO gen/use passes currently fail with an assert failure if there's a
critical edge whose source is an IndirectBr instruction and that edge
needs to be instrumented.

To avoid this in certain cases, split IndirectBr critical edges in the PGO
gen/use passes. This works for blocks with single indirectbr predecessors,
but not for those with multiple indirectbr predecessors (splitting an
IndirectBr critical edge isn't always possible.)

Reviewers: davidxl, xur

Reviewed By: davidxl

Subscribers: efriedma, llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D40699

llvm-svn: 320511
2017-12-12 19:07:43 +00:00
Alexey Bataev
195c97e220 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320510
2017-12-12 18:47:00 +00:00
Zhihao Yuan
bcde6e715e [libcxx] P0604, invoke_result and is_invocable
Summary:
Introduce a new form of `result_of` without function type encoding.

Rename and split `is_callable/is_nothrow_callable` into `is_invocable/is_nothrow_invocable/is_invocable_r/is_nothrow_invocable_r` (and associated types accordingly)

Change function type encoding of previous `is_callable/is_nothrow_callable` traits to conventional template type parameter lists.


Reviewers: EricWF, mclow.lists, bebuch

Reviewed By: EricWF, bebuch

Subscribers: lichray, bebuch, cfe-commits

Differential Revision: https://reviews.llvm.org/D38831

llvm-svn: 320509
2017-12-12 18:42:04 +00:00
Sanjoy Das
81a4a02cbc Revert "[X86] Flag BroadWell scheduler model as complete"
This reverts commit r320308.  r320308 crashes LLC, please see the llvm-commits
thread for a reproducer.

llvm-svn: 320508
2017-12-12 18:40:58 +00:00
Craig Topper
712a209db9 [X86] Add a couple TODOs about missing coverage/features motivated by D40335
D40335 was wanting to add FMSUBADD support, but it discovered that there are two pieces of code to make FMADDSUB and only one of those is tested. So I've asked that review to implement the one path until we get tests that test the existing code.

llvm-svn: 320507
2017-12-12 18:39:04 +00:00
Kelvin Li
af7c0ef435 Add --cuda-path to mock a CUDA Toolkit installation to avoid
unexpected error messages for incompatibility between the
default SM level and the support in the installed toolkit.

Differential Revision: https://reviews.llvm.org/D40996

llvm-svn: 320506
2017-12-12 18:33:39 +00:00
Nirav Dave
674d053d18 [X86] Cleanup type conversion of 64-bit load-store pairs.
Summary:
Simplify and generalize chain handling and search for 64-bit load-store pairs.
Nontemporal test now converts 64-bit integer load-store into f64 which it realizes directly instead of splitting into two i32 pairs.

Reviewers: craig.topper, spatel

Reviewed By: craig.topper

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40918

llvm-svn: 320505
2017-12-12 18:25:48 +00:00
Alexandre Ganea
757026dbe6 Test commit.
llvm-svn: 320504
2017-12-12 18:00:43 +00:00
Geoff Berry
60c431022e [MachineOperand][MIR] Add isRenamable to MachineOperand.
Summary:
Add isRenamable() predicate to MachineOperand.  This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand.  Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).

Reviewers: qcolombet, MatzeB, hfinkel

Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D39400

llvm-svn: 320503
2017-12-12 17:53:59 +00:00
Rafael Espindola
10bcc1cf90 Fix line endings. NFC.
llvm-svn: 320502
2017-12-12 17:37:01 +00:00
Alexey Bataev
6132a50d2a Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320499 again to resolve the problem with the
sanitizers bbots.

llvm-svn: 320501
2017-12-12 17:35:29 +00:00
Casey Carter
00c872f353 workaround PR 28385 in __find_exactly_one_checked
Fixes #35578.

Differential Revision: D41048

llvm-svn: 320500
2017-12-12 17:22:24 +00:00
Alexey Bataev
ca4c9a5246 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320499
2017-12-12 17:19:15 +00:00
Alexey Bataev
d19dbe6791 Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320496 to solve the problems with sanitizer
buildbots.

llvm-svn: 320498
2017-12-12 17:08:48 +00:00
Don Hinton
49777fa933 [cmake] Support moving debuginfo-tests to llvm/projects
Differential Revision: https://reviews.llvm.org/D40972

llvm-svn: 320497
2017-12-12 17:06:08 +00:00
Alexey Bataev
d0c3aeb200 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320496
2017-12-12 16:58:48 +00:00
Don Hinton
3a58f6716c [debuginfo-tests] Support moving debuginfo-tests to llvm/projects
Summary:
Add cmake and lit files needed to run these tests as an
external project.  Also, copy test_debuginfo.pl from llvm/utils since
it's only used here.  The copy in llvm/utils must be maintained as
long as bots continue to include debuginfo-tests in clang/test.

This patch depends on clang patch https://reviews.llvm.org/D41055.

Reviewers: zturner, aprantl

Reviewed By: aprantl

Subscribers: mgorny, llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D40971

llvm-svn: 320495
2017-12-12 16:54:20 +00:00
Don Hinton
f55db9caf4 [debuginfo-tests] Add support for moving debuginfo-tests from clang/test to llvm/projects or monorepo.
Summary:
The new version of debuginfo-tests will have it's own
lit.cfg.py file which is incompatible with the one in clang/test.
This change supports both the old and new versions, and can be used
until the bots actually move debuginfo-tests to either clang/test or
the monorepo.

This is a prerequisite for D40971.

Reviewers: zturner, aprantl

Subscribers: mgorny, JDevlieghere, llvm-commits, cfe-commits

Differential Revision: https://reviews.llvm.org/D41055

llvm-svn: 320494
2017-12-12 16:48:35 +00:00
Erich Keane
1a3b8fd8af Revert a part of 320489 that was submitted unintentionally.
llvm-svn: 320493
2017-12-12 16:22:31 +00:00
Simon Pilgrim
68f9accf51 [X86] Remove CompleteModel tags from CPU targets until we have better error checking (PR35636)
The checks we have for complete models are not great and miss many cases - e.g. in PR35636 it failed to recognise that only the first output (of 2) was actually tagged by the InstRW

Raised PR35639 and PR35643 as examples

llvm-svn: 320492
2017-12-12 16:12:53 +00:00
Alex Bradbury
c01db1ce8f [RISCV][NFC] Formatting fix in RISCVInstrInfo.td
llvm-svn: 320491
2017-12-12 16:10:21 +00:00
Alexey Bataev
c9f1d2e4a0 Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320488 because of the failed asan buildbots..

llvm-svn: 320490
2017-12-12 16:05:52 +00:00
Erich Keane
bd2197c0c1 Fix ICE when __has_unqiue_object_representations called with invalid decl
llvm-svn: 320489
2017-12-12 16:02:06 +00:00
Alexey Bataev
fb68c48a82 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320488
2017-12-12 15:54:49 +00:00
Alex Bradbury
9ed84c8ae8 [RISCV] Implement assembler pseudo instructions for RV32I and RV64I
Adds the assembler pseudo instructions of RV32I and RV64I which can
be mapped to a single canonical instruction. The missing pseudo
instructions (e.g., call, tail, ...) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

Currently, alias emission is disabled by default to keep the patch
minimal. Alias emission by default will be enabled in a subsequent
patch which also updates all affected tests. Note that this patch
should actually break the floating point MC tests. However, the
used FileCheck configuration is not tight enought to detect the
breakage.

Differential Revision: https://reviews.llvm.org/D40902

Patch by Mario Werner.

llvm-svn: 320487
2017-12-12 15:46:15 +00:00
Haojian Wu
4c1394d67d [clangd] Introduce a "Symbol" class.
Summary:
* The "Symbol" class represents a C++ symbol in the codebase, containing all the
  information of a C++ symbol needed by clangd. clangd will use it in clangd's
  AST/dynamic index and global/static index (code completion and code
  navigation).
* The SymbolCollector (another IndexAction) will be used to recollect the
  symbols when the source file is changed (for ASTIndex), or to generate
  all C++ symbols for the whole project.

In the long term (when index-while-building is ready), clangd should share a
same "Symbol" structure and IndexAction with index-while-building, but
for now we want to have some stuff working in clangd.

Reviewers: ioeric, sammccall, ilya-biryukov, malaperle

Reviewed By: sammccall

Subscribers: malaperle, klimek, mgorny, cfe-commits

Differential Revision: https://reviews.llvm.org/D40897

llvm-svn: 320486
2017-12-12 15:42:10 +00:00
Alexey Bataev
ca2a8cea2f Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320483 because of the failed Windows buildbots.

llvm-svn: 320485
2017-12-12 15:24:17 +00:00
Alex Bradbury
8bba6bfeef [RISCV] MC layer support for the instructions added in the privileged spec
Adds support for the instructions added in the RISC-V privileged ISA
(https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf):
uret, sret, mret, wfi, and sfence.vma.

Note from the committer: I made very minor formatting changes prior to commit, 
which didn't seem worth creating another review round-trip for.

Differential Revision: https://reviews.llvm.org/D40383

Patch by David Craven.

llvm-svn: 320484
2017-12-12 15:17:45 +00:00
Alexey Bataev
1daef8a667 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320483
2017-12-12 15:03:17 +00:00
Ilya Biryukov
ef3191fcfd [clangd] Removed unused variable. NFC
llvm-svn: 320482
2017-12-12 14:15:01 +00:00
Ayman Musa
c2eed926b0 [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction.
Recognize constant arrays with the following values:
  0x0, 0x1, 0x3, 0x7, 0xF, 0x1F, .... , 2^(size - 1) -1
where //size// is the size of the array.

the result of a load with index //idx// from this array is equivalent to the result of the following:
  (0xFFFFFFFF >> (sub 32, idx))             (assuming the array of type 32-bit integer).

And the result of an 'AND' operation on the returned value of such a load and another input, is exactly equivalent to the X86 BZHI instruction behavior.

See test cases in the LIT test for better understanding.

Differential Revision: https://reviews.llvm.org/D34141

llvm-svn: 320481
2017-12-12 14:13:51 +00:00
Anna Thomas
2dd9835f35 [InstComineLoadStoreAlloca] Optimize stores to GEP off null base
Summary:
Currently, in InstCombineLoadStoreAlloca, we have simplification
rules for the following cases:
  1. load off a null
  2. load off a GEP with null base
  3. store to a null

This patch adds support for the fourth case which is store into a
GEP with null base. Since this is UB as well (and directly analogous to
the load off a GEP with null base), we can substitute the stored val
with undef in instcombine, so that SimplifyCFG can optimize this code
into unreachable code.

Note: Right now, simplifyCFG hasn't been taught about optimizing
this to unreachable and adding an llvm.trap (this is already done for
the above 3 cases).

Reviewers: majnemer, hfinkel, sanjoy, davide

Reviewed by: sanjoy, davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41026

llvm-svn: 320480
2017-12-12 14:12:33 +00:00
Krasimir Georgiev
11ef531b5c [clang-format] Improve ObjC headers detection.
This patch improves detection of ObjC header files.
Right now many ObjC headers, especially short ones, are categorized as C/C++.

Way of filtering still isn't the best, as most likely it should be token-based.

Contributed by jolesiak!

llvm-svn: 320479
2017-12-12 13:43:59 +00:00