intel/llvm

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Manish Gupta 114ba722c1 [mlir][NVGPU] Handle native mma.sync and ldmatrix(x4) sizes

This patch handles native `mma.sync` sizes and enables issuing `ldmatrix` on
largest possible tiles for matrixB. It requires handling
`vector.extract_strided_slice` from vector to ngpu lowering.

Differential Revision: https://reviews.llvm.org/D135749

2022-10-19 17:10:21 -07:00

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benchmark/python

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[mlir][ods] Do not print default-valued attributes when the value is equal to the default

2022-10-17 13:57:36 -07:00

Introduce a ConditionallySpeculatable op interface

2022-10-12 10:56:12 -07:00

[mlir][NVGPU] Handle native mma.sync and ldmatrix(x4) sizes

2022-10-19 17:10:21 -07:00

[mlir][NVGPU] Handle native mma.sync and ldmatrix(x4) sizes

2022-10-19 17:10:21 -07:00

[mlir] switch the transform loop extension to use types

2022-10-11 09:55:23 +00:00

[mlir][NVGPU] Handle native mma.sync and ldmatrix(x4) sizes

2022-10-19 17:10:21 -07:00

Add ::mlir:: prefix to Attribute type in the generated code.

2022-10-17 22:14:26 -07:00

[mlir][sparse] Removing the DimLvlType and DimLevelFormat types

2022-10-18 15:47:40 -07:00

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.clang-format

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.clang-tidy

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CMakeLists.txt

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LICENSE.TXT

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README.md

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README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.