Manish Gupta 114ba722c1 [mlir][NVGPU] Handle native mma.sync and ldmatrix(x4) sizes ...

This patch handles native `mma.sync` sizes and enables issuing `ldmatrix` on
largest possible tiles for matrixB. It requires handling
`vector.extract_strided_slice` from vector to ngpu lowering.

Differential Revision: https://reviews.llvm.org/D135749

2022-10-19 17:10:21 -07:00

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Analysis

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AsmParser

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Bindings/Python

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Bytecode

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CAPI

[mlir][sparse] Use the runtime DimLevelType instead of a separate tablegen enum

2022-10-18 13:45:26 -07:00

Conversion

[mlir][NVGPU] Handle native mma.sync and ldmatrix(x4) sizes

2022-10-19 17:10:21 -07:00

Dialect

[mlir][NVGPU] Handle native mma.sync and ldmatrix(x4) sizes

2022-10-19 17:10:21 -07:00

ExecutionEngine

[mlir][sparse] Moving Enums.h into Dialect/SparseTensor/IR

2022-10-18 15:15:18 -07:00

Interfaces

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IR

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Parser

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Pass

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Reducer

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Rewrite

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Support

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TableGen

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Target

[mlir][llvm] Ordered traversal in LLVM IR import.

2022-10-19 12:57:09 +03:00

Tools

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Transforms

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CMakeLists.txt

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