It's worth noting that when the detection logic is inverted,
the boot ROM assumes the SD card is disconnected and skips
booting from it altogether.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
If the card is not connected at boot, force_jtag in
SYS_GRF_SOC_CON6 may remain set. This muxes DAT2/DAT3 over
to JTAG instead of SDMMC, preventing SD card operation in
4-bit mode.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
* ATF (BL31) from v1.40 to v1.45
* OP-TEE (BL32) from v1.13 to v1.15
* ddrbin from v1.12 to v1.16
* U-Boot SPL from v1.12 to v1.13
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
Latest EDK2 requires a proper RNG driver in order to use network boot
(CVE-2023-45237).
We ought to implement one, but for now bypass this check.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
This controller has the limitation that a single ADMA2 descriptor cannot
cross 128 MB boundaries and must be split.
This would require a patch in SdMmcPciHcDxe, but SDMA works fine for the
time being.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
This enables the upcoming SCMI support in ACPI and SD/MMC clock &
voltage control for Windows.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
Regions should be clearly delimited so attributes don't mix up.
Also ensure that the TF-A region containing SCMI shared memory is not
added to the UEFI map. This addresses an issue where attributes seem to
change at runtime and the mismatch leads to a loss of cache coherency
between EL3 and lower level accesses.
TF-A maps the shared memory as Device memory, so it needs to remain at
least non-cacheable here too (Device is not exactly possible due to
unaligned accesses from ArmScmiDxe). This could actually just be normal
write-back memory, since it's not shared with any external clients, but
whatever.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
Some devices that appear to have working CFG0 filtering (my VIA VL805)
do not actually like config cycles at B/D/F 01:01.0 and may screw up
further accesses (e.g. read 0xFFFFFFFF at valid locations) + eventually
hang up the bus after a few more attempts.
Checking for mirroring in this case is asking for trouble, but it seems
that trying 01:01.0 first and then 01:00.0 avoids the problem in UEFI.
OSes that rely on single device ECAM mode in ACPI are still going to
hang up the system, since they scan the entire affected bus.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
To deal with the broken ECAM on this platform, reuse some existing OS
workarounds:
- for Windows: "NXPMX6" OEM ID in FADT and split MCFG entries for root
port and main config space.
- for Linux: "AMAZON" OEM ID + "GRAVITON" OEM Table ID in MCFG. An
"AMZN0001" device with _UID matching the RC segment number returns the
root port's DBI address in _CRS.
Both workarounds filter device > 0 on primary and secondary buses of RP
to hide ghost and duplicate devices.
The compatibility mode used can be configured in the setup menu.
Default is "Auto (NXPMX6 + Single Device)", which selects the NXPMX6
mode when Windows is booted and the classic single device/bus mode for
other OSes, since it's the most compatible one.
Also move the PCIe and SATA SSDT definitions in DSDT and patch _STA
instead to disable the unnecessary controllers.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
Mux the TX clock source accordingly and initialize MCLK at 256 * 48000Hz
to fix playback speed in Windows.
RX is not configured yet.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
Lay groundwork to support:
- clocks from other CRU instances (e.g. PMU1CRU).
- gating and reset. Resets are separate due to them controlling not only
clocks but also peripheral blocks.
Also:
- validate input parameters
- fix PMU1CRU definitions
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
When a keyboard gets installed after connecting the USB controller
handles, ConPlatformDxe will check that its short-form device path
exists in the ConIn variable before enabling input from it.
This variable is missing at first boot, so adding the path after the
keyboard was already ignored means it won't be usable during BDS
countdown.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
Firstly, split up the Dw8250 serial lib into "full" and "debug"
versions. The full version is only used at SEC phase (PrePi) for setting
the specified baud rate, while the debug one is used everywhere else and
cannot reinitialize the UART.
To read the baud rate NV variable in SEC, introduce BaseVariableLib,
which is just a slightly modified FaultTolerantWritePei + VariablePei to
not use HOBs and PPIs, since they're not available this early.
Previous boot stages (DDR, TF-A, U-Boot SPL) are still hardcoded to
output at 1.5 Mbaud.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
Use gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorage* everywhere for
consistency.
This also fixes FTW, since its PCDs were previously set to wrong
addresses in the DSC.
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
